An Ultra-Energy-Efficient and High Accuracy ECG Classification Processor With SNN Inference Assisted by On-Chip ANN Learning

Towards Hardware Supported Domain Generalization in DNN-Based Edge Computing Devices for Health Monitoring

Deep neural network (DNN) models have shown remarkable success in many real-world scenarios, such as object detection and classification. Unfortunately, these models are not yet widely adopted in health monitoring due to exceptionally high requirements for model robustness and deployment in highly resource-constrained devices. In particular, the acquisition of biosignals, such as electrocardiogram (ECG), is subject to large variations between training and deployment, necessitating domain generalization (DG) for robust classification quality across sensors and patients. The continuous monitoring of ECG also requires the execution of DNN models in convenient wearable devices, which is achieved by specialized ECG accelerators with small form factor and ultra-low power consumption. However, combining DG capabilities with ECG accelerators remains a challenge. This article provides a comprehensive overview of ECG accelerators and DG methods and discusses the implication of the combination of both domains, such that multi-domain ECG monitoring is enabled with emerging algorithm-hardware co-optimized systems. Within this context, an approach based on correction layers is proposed to deploy DG capabilities on the edge. Here, the DNN fine-tuning for unknown domains is limited to a single layer, while the remaining DNN model remains unmodified. Thus, computational complexity (CC) for DG is reduced with minimal memory overhead compared to conventional fine-tuning of the whole DNN model. The DNN model-dependent CC is reduced by more than 2.5 compared to DNN fine-tuning at an average increase of F1 score by more than 20 % on the generalized target domain. In summary, this article provides a novel perspective on robust DNN classification on the edge for health monitoring applications.

Low-Power and Low-Cost AI Processor With Distributed-Aggregated Classification Architecture for Wearable Epilepsy Seizure Detection

Wearable devices with continuous monitoring capabilities are critical for the daily detection of epileptic seizures, as they provide users with accurate and comprehensible analytical results. However, current AI classifiers rely on a two-stage recognition process for continuous monitoring, which only reduces operation time but remains challenged by the high cost of additional hardware. To address this problem, this article proposes a novel fusion architecture for AI processors, which enables event-triggered cross-paradigm integration and computation. Our method introduces a distributed-aggregated classification architecture (D-ACA) that facilitates the reuse of hardware resources across two-stage recognition, thereby obviating the need for standby hardware and enhancing energy efficiency. Integrating a non-encoding biomedical circuit method based on spiking neural networks (SNNs), the architecture eliminates encoded neurons at the hardware level, significantly optimizing energy consumption and hardware resource utilization. Additionally, we develop a configurable and highly flexible control method that supports various neuron modules, enabling continuous detection of epileptic seizures and activating high-precision recognition upon event detection. Finally, we implement the design on the Xilinx ZCU 102 FPGA board, where the AI processor achieves a high classification accuracy of 98.1% while consuming extremely low classification energy (3.73 J per classification).

A Multi-Class ECG Signal Classifier Using a Binarized Depthwise Separable CNN with the Merged Convolution-Pooling Method

Binarized convolutional neural networks (bCNNs) are favored for the design of low-storage, low-power cardiac arrhythmia classifiers owing to their high weight compression rate. However, multi-class classification of ECG signals based on bCNNs is challenging due to the accuracy loss introduced by the binarization operation. In this paper, an effective multi-classifier system is proposed for electrocardiogram (ECG) signals using a binarized depthwise separable convolutional neural network (bDSCNN) with the merged convolution-pooling (MCP) method. The binarized depthwise separable convolution layer is adopted to reduce the increased number of parameters in multi-classification systems. Instead of operating convolution and pooling sequentially as in a traditional convolutional neural network (CNN), the MCP method merges pooling together with convolution layers to reduce the number of computations. To further reduce hardware resources, this work employs blockwise incremental calculation to eliminate redundant storage with computations. In addition, the R peak interval data are integrated with P-QRS-T features to improve the classification accuracy. The proposed bDSCNN model is evaluated on an Intel DE1-SoC field-programmable gate array (FPGA), and the experimental results demonstrate that the proposed system achieves a five-class classification accuracy of 96.61% and a macro-F1 score of 89.08%, along with a dynamic power dissipation of 20 μW for five-category ECG signal classification. The hardware resource usage of BRAM and LUTs plus REGs is reduced by at least 2.94 and 1.74 times, respectively, compared with existing ECG classifiers using bCNN methods.

HybMED: A Hybrid Neural Network Training Processor With Multi-Sparsity Exploitation for Internet of Medical Things

Cloud-based training and edge-based inference modes for Artificial Intelligence of Medical Things (AIoMT) applications suffer from accuracy degradation due to physiological signal variations among patients. On-chip learning can overcome this issue by online adaptation of neural network parameters for user-specific tasks. However, existing on-chip learning processors have limitations in terms of versatility, resource utilization, and energy efficiency. We propose HybMED, which is a novel neural signal processor that supports on-chip hybrid neural network training using a composite direct feedback alignment-based paradigm. HybMED is suitable for general-purpose health monitoring AIoMT devices. It improves resource utilization and area efficiency by the reconfigurable homogeneous core with heterogeneous data flow and enhances energy efficiency by exploiting sparsity at different granularities. The chip was fabricated by TSMC 40nm process and tested in multiple physiological signal processing tasks, demonstrating an average improvement in accuracy of 41.16% following online few-shot learning. The chip demonstrates an area efficiency of 1.17 GOPS/mm 2 and an energy efficiency of 1.58 TOPS/W. Compared to the previous state-of-the-art physiological signal processors with on-chip learning, the chip achieves a 65 × improvement in area efficiency and 1.48 × improvement in energy efficiency, respectively.

A Reconfigurable Near-Sensor Processor for Anomaly Detection in Limb Prostheses

This paper presents a reconfigurable near-sensor anomaly detection processor to real-time monitor the potential anomalous behaviors of amputees with limb prostheses. The processor is low-power, low-latency, and suitable for equipment on the prostheses and comprises a reconfigurable Variational Autoencoder (VAE), a scalable Self-Organizing Map (SOM) Array, and a window-size-adjustable Markov Chain, which can implement an integrated miniaturized anomaly detection system. With the reconfigurable VAE, the proposed processor can support up to 64 sensor sampling channels programmable by global configuration, which can meet the anomaly detection requirements in different scenarios. A scalable SOM array allows for the selection of different sizes based on the complexity of the data. Unlike traditional time accumulation-based anomaly detection methods, the Markov Chain is utilized to detect time-series-based anomalous data. The processor is designed and fabricated in a UMC 40-nm LP technology with a core area of 1.49 mm 2 and a power consumption of 1.81 mW. It achieves real-time detection performance with 0.933 average F1 Score for the FSP dataset within 24.22 μs, and 0.956 average F1 Score for the SFDLA-12 dataset within 30.48 μs. The energy dissipation of detection for each input feature is 43.84 nJ with the FSP dataset, and 55.17 nJ with the SFDLA-12 dataset. Compared with ARM Cortex-M4 and ARM Cortex-M33 microcontrollers, the processor achieves energy and area efficiency improvements ranging from 257 ×, 193 × and 11 ×, 8 ×, respectively.

Exploring the potential of spiking neural networks in biomedical applications: advantages, limitations, and future perspectives

In this paper, a comprehensive exploration is undertaken to elucidate the utilization of Spiking Neural Networks (SNNs) within the biomedical domain. The investigation delves into the experimentally validated advantages of SNNs in comparison to alternative models like LSTM, while also critically examining the inherent limitations of SNN classifiers or algorithms. SNNs exhibit distinctive advantages that render them particularly apt for targeted applications within the biomedical field. Over time, SNNs have undergone extensive scrutiny in realms such as neuromorphic processing, Brain-Computer Interfaces (BCIs), and Disease Diagnosis. Notably, SNNs demonstrate a remarkable affinity for the processing and analysis of biomedical signals, including but not limited to electroencephalogram (EEG), electromyography (EMG), and electrocardiogram (ECG) data. This paper initiates its exploration by introducing some of the biomedical applications of EMG, such as the classification of hand gestures and motion decoding. Subsequently, the focus extends to the applications of SNNs in the analysis of EEG and ECG signals. Moreover, the paper delves into the diverse applications of SNNs in specific anatomical regions, such as the eyes and noses. In the final sections, the paper culminates with a comprehensive analysis of the field, offering insights into the advantages, disadvantages, challenges, and opportunities introduced by various SNN models in the realm of healthcare and biomedical domains. This holistic examination provides a nuanced perspective on the potential transformative impact of SNN across a spectrum of applications within the biomedical landscape.

Demonstration of In-Memory Biosignal Analysis: Novel High-Density and Low-Power 3D Flash Memory Array for Arrhythmia Detection

Smart healthcare systems integrated with advanced deep neural networks enable real-time health monitoring, early disease detection, and personalized treatment. In this work, a novel 3D AND-type flash memory array with a rounded double channel for computing-in-memory (CIM) architecture to overcome the limitations of conventional smart healthcare systems: the necessity of high area and energy efficiency while maintaining high classification accuracy is proposed. The fabricated array, characterized by low-power operations and high scalability with double independent channels per floor, exhibits enhanced cell density and energy efficiency while effectively emulating the features of biological synapses. The CIM architecture leveraging the fabricated array achieves high classification accuracy (93.5%) for electrocardiogram signals, ensuring timely detection of potentially life-threatening arrhythmias. Incorporated with a simplified spike-timing-dependent plasticity learning rule, the CIM architecture is suitable for robust, area- and energy-efficient in-memory arrhythmia detection systems. This work effectively addresses the challenges of conventional smart healthcare systems, paving the way for a more refined healthcare paradigm.

An overview of brain-like computing: Architecture, applications, and future trends

With the development of technology, Moore's law will come to an end, and scientists are trying to find a new way out in brain-like computing. But we still know very little about how the brain works. At the present stage of research, brain-like models are all structured to mimic the brain in order to achieve some of the brain's functions, and then continue to improve the theories and models. This article summarizes the important progress and status of brain-like computing, summarizes the generally accepted and feasible brain-like computing models, introduces, analyzes, and compares the more mature brain-like computing chips, outlines the attempts and challenges of brain-like computing applications at this stage, and looks forward to the future development of brain-like computing. It is hoped that the summarized results will help relevant researchers and practitioners to quickly grasp the research progress in the field of brain-like computing and acquire the application methods and related knowledge in this field.