A Survey of Memristive Threshold Logic Circuits

Programmable Threshold Logic Implementations in a Memristor Crossbar Array

In this study, we demonstrate the implementation of programmable threshold logics using a 32 × 32 memristor crossbar array. Thanks to forming-free characteristics obtained by the annealing process, its accurate programming characteristics are presented by a 256-level grayscale image. By simultaneous subtraction between weighted sum and threshold values with a differential pair in an opposite way, 3-input and 4-input Boolean logics are implemented in the crossbar without additional reference bias. Also, we verify a full-adder circuit and analyze its fidelity, depending on the device programming accuracy. Lastly, we successfully implement a 4-bit ripple carry adder in the crossbar and achieve reliable operations by read-based logic operations. Compared to stateful logic driven by device switching, a 4-bit ripple carry adder on a memristor crossbar array can perform more reliably in fewer steps thanks to its read-based parallel logic operation.

Skyrmion based majority logic gate by voltage controlled magnetic anisotropy in a nanomagnetic device

Magnetic skyrmions are topologically protected spin textures and they are suitable for future logic-in-memory applications for energy-efficient, high-speed information processing and computing technologies. In this work, we have demonstrated skyrmion-based 3 bit majority logic gate using micromagnetic simulations. The skyrmion motion is controlled by introducing agatethat works on voltage controlled magnetic anisotropy. Here, the inhomogeneous magnetic anisotropy behaves as a tunable potential barrier/well that modulates the skyrmion trajectory in the structure for the successful implementation of the majority logic gate. In addition, several other effects such as skyrmion-skyrmion topological repulsion, skyrmion-edge repulsion, spin-orbit torque and skyrmion Hall effect have been shown to govern the logic functionalities. We have systematically presented the robust logic operations by varying the current density, magnetic anisotropy, voltage-controlled gate dimension and geometrical parameters of the logic device. The skyrmion Hall angle is monitored to understand the trajectory and stability of the skyrmion as a function of time in the logic device. The results demonstrate a novel method to achieve majority logic by using voltage controlled magnetic anisotropy which further opens up a new route for skyrmion-based low-power and high-speed computing devices.

Graphene/Ferroelectric (Ge-Doped HfO2) Adaptable Transistors Acting as Reconfigurable Logic Gates

We present an array of 225 field-effect transistors (FETs), where each of them has a graphene monolayer channel grown on a 3-layer deposited stack of 22 nm control HfO₂/5 nm Ge-HfO₂ intermediate layer/8 nm tunnel HfO₂/p-Si substrate. The intermediate layer is ferroelectric and acts as a floating gate. All transistors have two top gates, while the p-Si substrate is acting as a back gate. We show that these FETs are acting memtransistors, working as two-input reconfigurable logic gates with memory, the type of the logic gate depending only on the values of the applied gate voltages and the choice of a threshold current.

Recursive Threshold Logic-A Bioinspired Reconfigurable Dynamic Logic System With Crossbar Arrays

The neuron behavioral models are inspired by the principle of the firing of neurons, and weighted accumulation of charge for a given set of input stimuli. Biological neurons show dynamic behavior through its feedback and feedforward time-dependent responses. The principle of the firing of neurons inspires threshold logic design by applying threshold functions on the weight summation of inputs. In this article, we present a recursive threshold logic unit that uses the output feedback from standard threshold logic gates to emulate Boolean expressions in a time-sequenced manner. The Boolean expression is implemented with an analog resistive divider in memristive crossbars and a hard-threshold function designed with CMOS comparator for realizing the sums (OR) and products (AND) operators. The method benefits from reliable programming of the memristors in 1T1R crossbar configuration to suppress sneak path currents and thus enable larger crossbar sizes, which in turn allow a higher number of Boolean inputs. The reference threshold voltage for the decision comparators is tuned to implement AND and OR logic. The threshold value range is limited by the number of inputs to the crossbar. Simultaneously, the resistance of the memristors is kept constant at R_ON. The circuit's tolerance to the memristor variability and aging are analyzed, showing sufficient resilience. Also, the proposed recursive logic uses fewer cross-points, and has lower power dissipation than other memristive logic and CMOS implementation.

Memory devices and applications for in-memory computing

Traditional von Neumann computing systems involve separate processing and memory units. However, data movement is costly in terms of time and energy and this problem is aggravated by the recent explosive growth in highly data-centric applications related to artificial intelligence. This calls for a radical departure from the traditional systems and one such non-von Neumann computational approach is in-memory computing. Hereby certain computational tasks are performed in place in the memory itself by exploiting the physical attributes of the memory devices. Both charge-based and resistance-based memory devices are being explored for in-memory computing. In this Review, we provide a broad overview of the key computational primitives enabled by these memory devices as well as their applications spanning scientific computing, signal processing, optimization, machine learning, deep learning and stochastic computing.

Neuromemristive Circuits for Edge Computing: A Review

The volume, veracity, variability, and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks, and open problems in the field of neuromemristive circuits for edge computing.

Critical neuromorphic computing based on explosive synchronization

Synchronous oscillations in neuronal ensembles have been proposed to provide a neural basis for the information processes in the brain. In this work, we present a neuromorphic computing algorithm based on oscillator synchronization in a critical regime. The algorithm uses the high-dimensional transient dynamics perturbed by an input and translates it into proper output stream. One of the benefits of adopting coupled phase oscillators as neuromorphic elements is that the synchrony among oscillators can be finely tuned at a critical state. Especially near a critical state, the marginally synchronized oscillators operate with high efficiency and maintain better computing performances. We also show that explosive synchronization that is induced from specific neuronal connectivity produces more improved and stable outputs. This work provides a systematic way to encode computing in a large size coupled oscillator, which may be useful in designing neuromorphic devices.

Logic Computing with Stateful Neural Networks of Resistive Switches

Brain-inspired neural networks can process information with high efficiency, thus providing a powerful tool for pattern recognition and other artificial intelligent tasks. By adopting binary inputs/outputs, neural networks can be used to perform Boolean logic operations, thus potentially surpassing complementary metal-oxide-semiconductor logic in terms of area efficiency, execution time, and computing parallelism. Here, the concept of stateful neural networks consisting of resistive switches, which can perform all logic functions with the same network topology, is introduced. The neural network relies on physical computing according to Ohm's law, Kirchhoff 's law, and the ionic migration within an output switch serving as the highly nonlinear activation function. The input and output are nonvolatile resistance states of the devices, thus enabling stateful and cascadable logic operations. Applied voltages provide the synaptic weights, which enable the convenient reconfiguration of the same circuit to serve various logic functions. The neural network can solve all two-input logic operations with just one step, except for the exclusive-OR (XOR) needing two sequential steps. 1-bit full adder operation is shown to take place with just two steps and five resistive switches, thus highlighting the high efficiencies of space, time, and energy of logic computing with the stateful neural network.