Layer-Scale and Chip-Scale Transfer Techniques for Functional Devices and Systems: A Review.
NANOMATERIALS (BASEL, SWITZERLAND) 2021;
11:842. [PMID:
33806237 PMCID:
PMC8065746 DOI:
10.3390/nano11040842]
[Citation(s) in RCA: 6] [Impact Index Per Article: 2.0] [Reference Citation Analysis] [Abstract] [Key Words] [Grants] [Track Full Text] [Download PDF] [Figures] [Subscribe] [Scholar Register] [Received: 02/28/2021] [Revised: 03/16/2021] [Accepted: 03/22/2021] [Indexed: 02/07/2023]
Abstract
Hetero-integration of functional semiconductor layers and devices has received strong research interest from both academia and industry. While conventional techniques such as pick-and-place and wafer bonding can partially address this challenge, a variety of new layer transfer and chip-scale transfer technologies have been developed. In this review, we summarize such transfer techniques for heterogeneous integration of ultrathin semiconductor layers or chips to a receiving substrate for many applications, such as microdisplays and flexible electronics. We showed that a wide range of materials, devices, and systems with expanded functionalities and improved performance can be demonstrated by using these technologies. Finally, we give a detailed analysis of the advantages and disadvantages of these techniques, and discuss the future research directions of layer transfer and chip transfer techniques.
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