How does graphene grow on complex 3D morphologies?

Solid-diffusion-facilitated cleaning of copper foil improves the quality of CVD graphene

The quality of CVD-grown graphene is limited by the parallel nucleation of grains from surface impurities which leads to increased grain boundary densities. Currently employed cleaning methods cannot completely remove surface impurities since impurity diffusion from the bulk to the surface occurs during growth. We here introduce a new method to remove impurities not only on the surface but also from the bulk. By employing a solid cap during annealing that acts as a sink for impurities and leads to an enhancement of copper purity throughout the catalyst thickness. The high efficiency of the solid-diffusion-based transport pathway results in a drastic decrease in the surface particle concentration in a relatively short time, as evident in AFM and SIMS characterization of copper foils. Graphene grown on those substrates displays enhanced grain sizes and room-temperature, large-area carrier mobilities in excess of 5000 cm²/Vs which emphasizes the suitability of our approach for future graphene applications.

Ink-jet patterning of graphene by cap assisted barrier-guided CVD

Barrier-guided CVD growth could provide a new route to printed electronics by combining high quality 2D materials synthesis with scalable and cost-effective deposition methods. Unfortunately, we observe the limited stability of the barrier at growth conditions which results in its removal within minutes due to hydrogen etching. This work describes a route towards enhancing the stability of an ink-jet deposited barrier for high resolution patterning of high quality graphene. By modifying the etching kinetics under confinement, the barrier film could be stabilized and high resolution barriers could be retained even after 6 hours of graphene growth. Thus produced microscopic graphene devices exhibited an increase in conductivity by 6 orders of magnitude and a decrease in defectiveness by 48 times yielding performances that are superior to devices produced by traditional lithographical patterning which indicates the potential of our approach for future electronic applications.

High-resolution graphene patterning through ink-jet deposition of a barrier and subsequent CVD is achieved by a confinement-assisted growth process.