Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs

Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (V_d = 10 mV) and current drive up to 40 μA/wire (V_d = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.

Physics and performances of III-V nanowire broken-gap heterojunction TFETs using an efficient tight-binding mode-space NEGF model enabling million-atom nanowire simulations

We report the capability to simulate in a quantum-mechanical atomistic fashion record-large nanowire devices, featuring several hundred to millions of atoms and a diameter up to 18.2 nm. We have employed a tight-binding mode-space NEGF technique demonstrating by far the fastest (up to 10 000  ×  faster) but accurate (error  <  1%) atomistic simulations to date. Such technique and capability opens new avenues to explore and understand the physics of nanoscale and mesoscopic devices dominated by quantum effects. In particular, our method addresses in an unprecedented way the technologically-relevant case of band-to-band tunneling (BTBT) in III-V nanowire broken-gap heterojunction tunnel-FETs (HTFETs). We demonstrate an accurate match of simulated BTBT currents to experimental measurements in a 12 nm diameter InAs NW and in an InAs/GaSb Esaki tunneling diode. We apply our TB MS simulations and report the first in-depth atomistic study of the scaling potential of III-V GAA nanowire HTFETs including the effect of electron-phonon scattering and discrete dopant impurity band tails, quantifying the benefits of this technology for low-power low-voltage CMOS applications.

Precursor evaluation for in situ InP nanowire doping

The use of tetraethyltin (TESn) and dimethylzinc (DMZn) as in situ n- and p-dopant precursors during particle-assisted growth of InP nanowires is reported. Gate voltage dependent transport measurements demonstrate that the nanowires can be predictably synthesized as either n- or p-type. These doped nanowires can be characterized based on their electric field response and we find that n-type doping scales over a range from 10(17) to 10(19) cm(-3) with increasing input TESn dopant molar fraction. On the other hand, the p-type doping using DMZn saturates at low levels, probably related to a strong increase in nanowire growth rate with increasing DMZn molar fractions. By optimizing growth conditions with respect to tapering, axial pn-junctions exhibiting rectifying behavior were fabricated. The pn-junctions can be operated as light emitting diodes.