On the Aging of OTFTs and Its Impact on PUFs Reliability

Given the current maturity of printed technologies, Organic Thin-Film Transistors (OTFT) still show high initial variability, which can be beneficial for its exploitation in security applications. In this work, the process-related variability and aging of commercial OTFTs have been characterized to evaluate the feasibility of OTFTs-based Physical Unclonable Functions (PUFs) implementation. For our devices, ID-based PUFs show good uniformity and uniqueness. However, PUFs' reliability could be compromised because of the observed transient and aging effects in the OTFTs, which could hinder the reproducibility of the generated fingerprints. A systematic study of the aging of OTFTs has been performed to evaluate the PUFs' reliability. Our results suggest that the observed transient and aging effects could be mitigated so that the OTFTs-based PUFs' reliability could be improved.

A Review of Reliability in Gate-All-Around Nanosheet Devices

The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, coupled with aggressive pitch scaling, can give rise to reliability challenges. In this article, we present a review of the key reliability mechanisms in GAA NS FET, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide (Gox) time-dependent dielectric breakdown (TDDB), and middle-of-line (MOL) TDDB. We aim to not only underscore the unique reliability attributes inherent to NS architecture but also provide a holistic view of the status and prospects of NS reliability, taking into account the challenges posed by future scaling.

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (Vnom≤Vstress≤1.3Vnom and 25°C≤Tstress≤115°C) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50% and 70% of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1%, which is a first indicator proving the FPGAs' good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA.

Revealing the Mechanism of the Bias Temperature Instability Effect of p-GaN Gate HEMTs by Time-Dependent Gate Breakdown Stress and Fast Sweeping Characterization

The bias temperature instability (BTI) effect of p-GaN gate high-electron-mobility transistors (HEMTs) is a serious problem for reliability. To uncover the essential cause of this effect, in this paper, we precisely monitored the shifting process of the threshold voltage (V_TH) of HEMTs under BTI stress by fast sweeping characterizations. The HEMTs without time-dependent gate breakdown (TDGB) stress featured a high V_TH shift of 0.62 V. In contrast, the HEMT that underwent 424 s of TDGB stress clearly saw a limited V_TH shift of 0.16 V. The mechanism is that the TDGB stress can induce a Schottky barrier lowering effect on the metal/p-GaN junction, thus boosting the hole injection from the gate metal to the p-GaN layer. This hole injection eventually improves the V_TH stability by replenishing the holes lost under BTI stress. It is the first time that we experimentally proved that the BTI effect of p-GaN gate HEMTs was directly dominated by the gate Schottky barrier that impeded the hole supply to the p-GaN layer.

Microchip Health Monitoring System Using the FLL Circuit

Here a solution for a Microchip Health Monitoring (MHM) system using MTOL (Multi-Temperature Operational Life) reliability testing assessment data is proposed. The module monitors frequency degradation over time compared to lab tested data. Since trends in performance degradation in recently developed devices have transitioned from multiple failure mechanisms to a single dominant failure mechanism, development of the monitor is greatly simplified. The monitor uses a novel circuit customized to deliver optimum accuracy by combining the concepts of ring oscillator (RO) and phase locked loop (PLL) circuits. The modified circuit proposed is a new form of the frequency locked loop (FLL) circuit. We demonstrate that the collection of frequency degradation data from the ring circuits of each test produces Weibull distributions with steep slopes. This implies that the monitor can predict accurate end-of-life (EOL) predictions at early stages of chip degradations. The design of the microchip health monitoring system projected in this work can have great benefit in all systems using FPGA and ASIC devices.

Peroral endoscopic myotomy for the treatment of achalasia: an international prospective multicenter study

Pilot studies have indicated that peroral endoscopic myotomy (POEM) might be a safe and effective treatment for achalasia. We performed a prospective, international, multicenter study to determine the outcomes of 70 patients who underwent POEM at 5 centers in Europe and North America. Three months after POEM, 97% of patients were in symptom remission (95% confidence interval, 89%-99%); symptom scores were reduced from 7 to 1 (P < .001) and lower esophageal sphincter pressures were reduced from 28 to 9 mm Hg (P < .001). The percentage of patients in symptom remission at 6 and 12 months was 89% and 82%, respectively. POEM was found to be an effective treatment for achalasia after a mean follow-up period of 10 months.