Thermally Assisted Nonvolatile Memory in Monolayer MoS2 Transistors

Manipulation of the electrical and memory properties of MoS2 field-effect transistors by highly charged ion irradiation

Field-effect transistors based on molybdenum disulfide (MoS2) exhibit a hysteresis in their transfer characteristics, which can be utilized to realize 2D memory devices. This hysteresis has been attributed to charge trapping due to adsorbates, or defects either in the MoS2 lattice or in the underlying substrate. We fabricated MoS2 field-effect transistors on SiO2/Si substrates, irradiated these devices with Xe30+ ions at a kinetic energy of 180 keV to deliberately introduce defects and studied the resulting changes of their electrical and hysteretic properties. We find clear influences of the irradiation: while the charge carrier mobility decreases linearly with increasing ion fluence (up to only 20% of its initial value) the conductivity actually increases again after an initial drop of around two orders of magnitude. We also find a significantly reduced n-doping (≈1012 cm-2) and a well-developed hysteresis after the irradiation. The hysteresis height increases with increasing ion fluence and enables us to characterize the irradiated MoS2 field-effect transistor as a memory device with remarkably longer relaxation times (≈ minutes) compared to previous works.

Thermally Driven Multilevel Non-Volatile Memory with Monolayer MoS2 for Brain-Inspired Artificial Learning

The demands of modern electronic components require advanced computing platforms for efficient information processing to realize in-memory operations with a high density of data storage capabilities toward developing alternatives to von Neumann architectures. Herein, we demonstrate the multifunctionality of monolayer MoS₂ memtransistors, which can be used as a high-geared intrinsic transistor at room temperature; however, at a high temperature (>350 K), they exhibit synaptic multilevel memory operations. The temperature-dependent memory mechanism is governed by interfacial physics, which solely depends on the gate field modulated ion dynamics and charge transfer at the MoS₂/dielectric interface. We have proposed a non-volatile memory application using a single Field Effect Transistor (FET) device where thermal energy can be ventured to aid the memory functions with multilevel (3-bit) storage capabilities. Furthermore, our devices exhibit linear and symmetry in conductance weight updates when subjected to electrical potentiation and depression. This feature has enabled us to attain a high classification accuracy while training and testing the Modified National Institute of Standards and Technology datasets through artificial neural network simulation. This work paves the way toward reliable data processing and storage using 2D semiconductors with high-packing density arrays for brain-inspired artificial learning.

Gate-voltage-induced reversible electrical phase transitions in Mo0.67W0.33Se2 devices

Tunable electrical phase transitions based on the structural and quantum-state phase transitions in two-dimensional transition-metal dichalcogenides have attracted attention in both semiconducting electronics and quantum electronics applications. Here, we report gate-voltage-induced reversible electrical phase transitions in Mo_0.67W_0.33Se₂ (MoWSe) field-effect transistors prepared on SiO₂/Si substrates. In gate-induced depletion regions of the 2H phase, an electrical current resumes flow at 150 K < T < 200 K with decreasing T irrespective of the layer number (n) for MoWSe when n < 20. The newly appearing electron-doped-type conducting channel again enters the 2H-phase region when the back-gate voltage increases, accompanied by the negative differential transconductance for four-layer and monolayer devices or by a deflection point in the transfer curves for a multilayer device. The thermal activation energies of the new conducting and 2H-phase branches differ by one order of magnitude at the same gate voltage for both the four-layer and monolayer cases, indicating that the electrical band at the Fermi level was modified. The hysteresis measurements for the gate voltage were performed with a five-layer device, which confirms the reversible electrical transition behavior. The possible origins of the nucleated conducting phase in the depletion region of the 2H phase of MoWSe are discussed.

Defect Engineering in Thickness-Controlled Bi2O2Se-Based Transistors by Argon Plasma Treatment

We present a simple, effective, and controllable method to uniformly thin down the thickness of as-exfoliated two-dimensional Bi₂O₂Se nanoflakes using Ar⁺ plasma treatment. Atomic force microscopy (AFM) images and Raman spectra indicate that the surface morphology and crystalline quality of etched Bi₂O₂Se nanoflakes remain almost unaffected. X-ray photoelectron spectra (XPS) indicate that the O and Se vacancies created during Ar⁺ plasma etching on the top surface of Bi₂O₂Se nanoflakes are passivated by forming an ultrathin oxide layer with UV O₃ treatment. Moreover, a bottom-gate Bi₂O₂Se-based field-effect transistor (FET) was constructed to research the effect of thicknesses and defects on electronic properties. The on-current/off-current (I_on/I_off) ratio of the Bi₂O₂Se FET increases with decreasing Bi₂O₂Se thickness and is further improved by UV O₃ treatment. Eventually, the thickness-controlled Bi₂O₂Se FET achieves a high I_on/I_off ratio of 6.0 × 10⁴ and a high field-effect mobility of 5.7 cm² V^-1 s^-1. Specifically, the variation trend of the I_on/I_off ratio and the electronic transport properties for the bottom-gate Bi₂O₂Se-based FET are well described by a parallel resistor model (including bulk, channel, and defect resistance). Furthermore, the I_ds-V_gs hysteresis and its inversion with UV irradiation were observed. The pulsed gate and drain voltage measurements were used to extract trap time constants and analyze the formation mechanism of different hysteresis. Before UV irradiation, the origin of clockwise hysteresis is attributed to the charge trapping/detrapping of defects at the Bi₂O₂Se/SiO₂ interface and in the Bi₂O₂Se bulk. After UV irradiation, the large anticlockwise hysteresis is mainly due to the tunneling between deep-level oxygen defects in SiO₂ and p⁺⁺-Si gate, which implies the potential in nonvolatile memory.

Electrically and Optically Controllable p-n Junction Memtransistor Based on an Al2 O3 Encapsulated 2D Te/ReS2 van der Waals Heterostructure

The exploration of memtransistors as a combination of a memristor and a transistor has recently attracted intensive attention because it offers a promising candidate for next-generation multilevel nonvolatile memories and synaptic devices. However, the present state-of-the-art memtransistors, which are based on a single material, such as MoS₂ or perovskite, exhibit a relatively low switching ratio, require extremely high electric fields to modulate bistable resistance states and do not perform multifunctional operations. Here, the realization of an electrically and optically controllable p-n junction memtransistor using an Al₂ O₃ encapsulated 2D Te/ReS₂ van der Waals heterostructure is reported. The hybrid memtransistor shows a reversible bipolar resistance switching behavior between a low resistance state and a high resistance state with a high switching ratio up to 10⁶ at a low operating voltage (<10 V), high cycling endurance, and long retention time. Moreover, multiple resistance states are achieved by applying different bias voltages, gate voltages, or light powers. In addition, logical operations, including the inverter and AND/OR gates, and synaptic activities are performed by controlling the optical and electrical inputs. The work offers a novel strategy for the reliable fabrication of p-n junction memtransistors for multifunctional devices and neuromorphic applications.

Emerging 2D Memory Devices for In-Memory Computing

It is predicted that the conventional von Neumann computing architecture cannot meet the demands of future data-intensive computing applications due to the bottleneck between the processing and memory units. To try to solve this problem, in-memory computing technology, where calculations are carried out in situ within each nonvolatile memory unit, has been intensively studied. Among various candidate materials, 2D layered materials have recently demonstrated many new features that have been uniquely exploited to build next-generation electronics. Here, the recent progress of 2D memory devices is reviewed for in-memory computing. For each memory configuration, their operation mechanisms and memory characteristics are described, and their pros and cons are weighed. Subsequently, their versatile applications for in-memory computing technology, including logic operations, electronic synapses, and random number generation are presented. Finally, the current challenges and potential strategies for future 2D in-memory computing systems are also discussed at the material, device, circuit, and architecture levels. It is hoped that this manuscript could give a comprehensive review of 2D memory devices and their applications in in-memory computing, and be helpful for this exciting research area.

Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS2 Field-Effect Transistors

Clockwise to anticlockwise hysteresis crossover in current-voltage transfer characteristics of field-effect transistors (FETs) with graphene and MoS₂ channels holds significant promise for nonvolatile memory applications. However, such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS₂ FETs using a gate-drain underlap design to induce a differential response from traps near the MoS₂-HfO₂ channel-gate dielectric interface, also referred to as border traps, to applied gate bias. The appearance of trap-driven anticlockwise hysteresis at high gate voltages in underlap FETs can be unambiguously attributed to the presence of an underlap since transistors with and without the underlap region were fabricated on the same MoS₂ channel flake. The underlap design also enables room temperature tuning of the anticlockwise hysteresis window (by 140×) as well as the crossover gate voltage (by 2.6×) with applied drain bias and underlap length. Comprehensive measurements of the transfer curves in ambient and vacuum conditions at varying sweep rates and temperatures (RT, 45 °C, and 65 °C) help segregate the quantitative contributions of adsorbates, interface traps, and bulk HfO₂ traps to the clockwise and anticlockwise hysteresis.

Metal-Contact Improvement in a Multilayer WSe2 Transistor through Strong Hot Carrier Injection

Hot carrier injection (HCI), occurring when the horizontal electric field is strongly applied, usually affects the degradation of nanoelectronic devices. In addition, metal contacts play a significant role in nanoelectronic devices. In this study, Schottky contacts in multilayer tungsten diselenide (WSe₂) field-effect transistors (FETs) by hot carrier injection (HCI), occurring when a high drain voltage is applied, is investigated. A small number of hot carriers with high energy reduces the Schottky barrier height and improves the performance of FETs effectively rather than damaging the channel. Thermal annealing at the end of the fabrication process increases device performance by causing interfacial reactions of the source/drain electrodes. HCI causes a significant enhancement in the local asymmetry, especially in the subthreshold region. The subthreshold swing (SS) of the thermally annealed FETs is significantly improved from 9.66 to 0.562 V dec^-1 through the energy of HCI generated by a strong horizontal electric field. In addition, the contact resistances (R_SD), also called series resistances, extracted by a four-probe measurement and a Y-function method were also improved by decreasing to a 10th through the energy of HCI. To understand the asymmetrical characteristics of the channel after the stress, we performed electrical analysis, electrostatic force microscopy (EFM), and Raman spectroscopy.

Tailoring the transfer characteristics and hysteresis in MoS2 transistors using substrate engineering

We demonstrate a novel form of transfer characteristics in substrate engineered MoS2 field effect transistors. Robust hysteresis with stable threshold voltages and a large gate voltage window is observed, which is suppressed at low temperatures. We analyse the dependence of the device characteristics on gate voltage range, gate stressing and sweep rates. We infer that the hysteresis originates from artificially created charged traps near the MoS2-SiO2 interface. These charge traps act as long range Coulomb scatterers and are screened at high carrier densities. The hysteresis is strongly suppressed in measurements on wafers devoid of the substrate treatment, providing a new extrinsic route to carefully tune the transfer characteristics.

Real-time effect of electron beam on MoS2 field-effect transistors

Irradiation of MoS₂ field-effect transistors (FETs) fabricated on Si/SiO₂ substrates with electron beams (e-beams) below 30 keV creates electron-hole pairs (EHP) in the SiO₂, which increase the interface trap density (N_it ) and change the current path in the channel, resulting in performance changes. In situ measurements of the electrical characteristics of the FET performed using a nano-probe system mounted inside a scanning electron microscope show that e-beam irradiation enables both multilayer and monolayer MoS₂ channels act as conductors. The e-beams mostly penetrate the channel owing to their large kinetic energy, while the EHPs formed in the SiO₂ layer can contribute to the conductance by flowing into the MoS₂ channel or inducing the gate bias effect. The analysis of the device parameters in the initial state and the vent-evacuation state after e-beam irradiation can clarify the effect of the interplay between the e-beam-induced EHPs and ambient adsorbates on the carrier behavior, which depends on the thickness of the MoS₂ layer. DC and low frequency noise analysis reveals that the e-beam-induced EHPs increase N_it from 10⁹-10¹⁰ to 10¹¹ cm^-2 eV^-1 in both monolayer and multilayer devices, while the interfacial Coulomb scattering parameter α_SC increases by three times in the monolayer and decreases to one-tenth of its original value in the multilayer. In other words, an MoS₂ layer with a thickness of ∼30 nm is less sensitive to adsorbates by surface screening. Thus, the carrier mobility in the monolayer device decreases from 45.7 to 40 cm² V^-1 s^-1, while in the 30 nm-thick multilayer device, it increases from 4.9 to 5.6 cm² V^-1 s^-1. This is further evidenced by simulations of the distribution of interface traps and channel carriers in the MoS₂ FET before and after e-beam irradiation, demonstrating that Coulomb scattering decreases as the effective channel moves away from the interface.

Two-Dimensional Near-Atom-Thickness Materials for Emerging Neuromorphic Devices and Applications

Two-dimensional (2D) layered materials and their heterostructures have recently been recognized as promising building blocks for futuristic brain-like neuromorphic computing devices. They exhibit unique properties such as near-atomic thickness, dangling-bond-free surfaces, high mechanical robustness, and electrical/optical tunability. Such attributes unattainable with traditional electronic materials are particularly promising for high-performance artificial neurons and synapses, enabling energy-efficient operation, high integration density, and excellent scalability. In this review, diverse 2D materials explored for neuromorphic applications, including graphene, transition metal dichalcogenides, hexagonal boron nitride, and black phosphorous, are comprehensively overviewed. Their promise for neuromorphic applications are fully discussed in terms of material property suitability and device operation principles. Furthermore, up-to-date demonstrations of neuromorphic devices based on 2D materials or their heterostructures are presented. Lastly, the challenges associated with the successful implementation of 2D materials into large-scale devices and their material quality control will be outlined along with the future prospect of these emergent materials.

Neuromorphic nanoelectronic materials

Memristive and nanoionic devices have recently emerged as leading candidates for neuromorphic computing architectures. While top-down fabrication based on conventional bulk materials has enabled many early neuromorphic devices and circuits, bottom-up approaches based on low-dimensional nanomaterials have shown novel device functionality that often better mimics a biological neuron. In addition, the chemical, structural and compositional tunability of low-dimensional nanomaterials coupled with the permutational flexibility enabled by van der Waals heterostructures offers significant opportunities for artificial neural networks. In this Review, we present a critical survey of emerging neuromorphic devices and architectures enabled by quantum dots, metal nanoparticles, polymers, nanotubes, nanowires, two-dimensional layered materials and van der Waals heterojunctions with a particular emphasis on bio-inspired device responses that are uniquely enabled by low-dimensional topology, quantum confinement and interfaces. We also provide a forward-looking perspective on the opportunities and challenges of neuromorphic nanoelectronic materials in comparison with more mature technologies based on traditional bulk electronic materials.

Gate-Tunable Thermal Metal-Insulator Transition in VO2 Monolithically Integrated into a WSe2 Field-Effect Transistor

Vanadium dioxide (VO₂) shows promise as a building block of switching and sensing devices because it undergoes an abrupt metal-insulator transition (MIT) near room temperature, where the electrical resistivity changes by orders of magnitude. A challenge for versatile applications of VO₂ is to control the MIT by gating in the field-effect device geometry. Here, we demonstrate a gate-tunable abrupt switching device based on a VO₂ microwire that is monolithically integrated with a two-dimensional (2D) tungsten diselenide (WSe₂) semiconductor by van der Waals stacking. We fabricated the WSe₂ transistor using the VO₂ wire as the drain contact, titanium as the source contact, and hexagonal boron nitride as the gate dielectric. The WSe₂ transistor was observed to show ambipolar transport, with higher conductivity in the electron branch. The electron current increases continuously with gate voltage below the critical temperature of the MIT of VO₂. Near the critical temperature, the current shows an abrupt and discontinuous jump at a given gate voltage, indicating that the MIT in the contacting VO₂ is thermally induced by gate-mediated self-heating. Our results have paved the way for the development of VO₂-based gate-tunable devices by the van der Waals stacking of 2D semiconductors, with great potential for electronic and photonic applications.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 10⁶ times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Negative Differential Conductance & Hot-Carrier Avalanching in Monolayer WS2 FETs

The high field phenomena of inter-valley transfer and avalanching breakdown have long been exploited in devices based on conventional semiconductors. In this Article, we demonstrate the manifestation of these effects in atomically-thin WS₂ field-effect transistors. The negative differential conductance exhibits all of the features familiar from discussions of this phenomenon in bulk semiconductors, including hysteresis in the transistor characteristics and increased noise that is indicative of travelling high-field domains. It is also found to be sensitive to thermal annealing, a result that we attribute to the influence of strain on the energy separation of the different valleys involved in hot-electron transfer. This idea is supported by the results of ensemble Monte Carlo simulations, which highlight the sensitivity of the negative differential conductance to the equilibrium populations of the different valleys. At high drain currents (>10 μA/μm) avalanching breakdown is also observed, and is attributed to trap-assisted inverse Auger scattering. This mechanism is not normally relevant in conventional semiconductors, but is possible in WS₂ due to the narrow width of its energy bands. The various results presented here suggest that WS₂ exhibits strong potential for use in hot-electron devices, including compact high-frequency sources and photonic detectors.

Progress on Electronic and Optoelectronic Devices of 2D Layered Semiconducting Materials

2D layered semiconducting materials (2DLSMs) represent the thinnest semiconductors, holding many novel properties, such as the absence of surface dangling bonds, sizable band gaps, high flexibility, and ability of artificial assembly. With the prospect of bringing revolutionary opportunities for electronic and optoelectronic applications, 2DLSMs have prospered over the past twelve years. From materials preparation and property exploration to device applications, 2DLSMs have been extensively investigated and have achieved great progress. However, there are still great challenges for high-performance devices. In this review, we provide a brief overview on the recent breakthroughs in device optimization based on 2DLSMs, particularly focussing on three aspects: device configurations, basic properties of channel materials, and heterostructures. The effects from device configurations, i.e., electrical contacts, dielectric layers, channel length, and substrates, are discussed. After that, the affect of the basic properties of 2DLSMs on device performance is summarized, including crystal defects, crystal symmetry, doping, and thickness. Finally, we focus on heterostructures based on 2DLSMs. Through this review, we try to provide a guide to improve electronic and optoelectronic devices of 2DLSMs for achieving practical device applications in the future.