Implementation of Convolutional Neural Networks in Memristor Crossbar Arrays with Binary Activation and Weight Quantization

Wordline Input Bias Scheme for Neural Network Implementation in 3D-NAND Flash

In this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs). The approach leverages the velocity saturation effect in short-channel MOSFETs, which enables a linear increase in drain current with respect to gate voltage in the saturation region. A NAND flash array with a TANOS (TiN/Al2O3/Si3N4/SiO2/poly-Si) gate stack was fabricated, and its electrical and reliability characteristics were evaluated. Output characteristics of short-channel (L = 1 µm) and long-channel (L = 50 µm) devices were compared, confirming the linear behavior of short-channel devices due to velocity saturation. In the proposed system, analog WL voltages serve as inputs, and the summed bitline (BL) currents represent the outputs. Each synaptic weight is implemented using two paired devices, and each WL layer corresponds to a fully connected (FC) layer, enabling efficient vector-matrix multiplication (VMM). MNIST pattern recognition is conducted, demonstrated only a 0.32% accuracy drop for the short-channel device compared to the ideal linear case, and 0.95% degradation under 0.5 V threshold variation, while maintaining robustness. These results highlight the strong potential of 3D-NAND flash memory, which offers high integration density and technological maturity, for neuromorphic computing applications.

Flexible self-rectifying synapse array for energy-efficient edge multiplication in electrocardiogram diagnosis

Edge computing devices, which generate, collect, process, and analyze data near the source, enhance the data processing efficiency and improve the responsiveness in real-time applications or unstable network environments. To be utilized in wearable and skin-attached electronics, these edge devices must be compact, energy efficient for use in low-power environments, and fabricable on soft substrates. Here, we propose a flexible memristive dot product engine (f-MDPE) designed for edge use and demonstrate its feasibility in a real-time electrocardiogram (ECG) monitoring system. The f-MDPE comprises a 32 × 32 crossbar array embodying a low-temperature processed self-rectifying charge trap memristor on a flexible polyimide substrate and exhibits high uniformity and robust electrical and mechanical stability even under 5-mm bending conditions. Then, we design a neural network training algorithm through hardware-aware approaches and conduct real-time edge ECG diagnosis. This approach achieved an ECG classification accuracy of 93.5%, while consuming only 0.3% of the energy compared to digital approaches, highlighting the strong potential of this approach for emerging edge neuromorphic hardware.

All-Electrical Control of Spin Synapses for Neuromorphic Computing: Bridging Multi-State Memory with Quantization for Efficient Neural Networks

The development of energy-efficient, brain-inspired neuromorphic computing demands advanced memory devices capable of mimicking synaptic behavior to achieve high accuracy and adaptability. In this study, three types of all-electrically controlled, field-free spin synapse devices designed with unique spintronic structures presented: the Néel orange-peel effect, interlayer Dzyaloshinskii-Moriya interaction (i-DMI), and tilted anisotropy. To systematically evaluate their neuromorphic potential, a benchmarking framework is introduced that characterizes cycle-to-cycle (CTC) variation, a critical factor for reliable synaptic weight updates. Among these designs, the tilted anisotropy device achieves an 11-state memory with minimal CTC variation (2%), making it particularly suited for complex synaptic emulation. Through comprehensive benchmarking, this multi-state device in convolutional neural networks (CNNs) using post-training quantization is implemented. Results indicate that per-channel quantization, particularly with the min-max and mean squared error (MSE) observers, enhances classification accuracy on the CIFAR-10 dataset, achieving up to 81.51% and 81.12% in ResNet-18-values that closely approach the baseline accuracy. This evaluation underscores the potential of field-free spintronic synapses in neuromorphic architectures, offering an area-efficient solution that integrates multi-state functionality with robust switching performance. The findings highlight the promise of these devices in advancing neuromorphic computing, contributing to energy-efficient, high-performance systems inspired by neural processes.

High Rectification Ratio Self-Rectifying Memristor Crossbar Array for Convolutional Neural Network Operations

Oxide-based self-rectifying memristors have emerged as promising candidates for the construction of neural networks, owing to their advantageous features such as high-density integration, low power consumption, 3D stackability, straightforward fabrication processes, and compatibility with complementary metal-oxide-semiconductor (CMOS) technology. Notwithstanding these merits, there remains considerable scope for the suppression of parasitic currents in large-scale memristor arrays, which poses a notable challenge in the development of extensive neural networks capable of executing intricate computational tasks. This study introduces a 1 kbit self-rectifying memristor array based on Pt/HfO2/Ti structural units. Individual devices in this array not only exhibit switching ratios exceeding 103, but also maintain rectification ratios greater than 105, and their excellent negative rectification performance effectively suppresses latent path currents in the array. Moreover, the convolutional calculation logic and forward inference process of 8-bit neural networks are demonstrated based on this array, which verifies the feasibility of using arrays to simulate convolutional neural networks for all hardware operations. Ultimately, a complete convolutional neural network system is constructed, the system achieving a recognition rate of up to 98% in the handwriting recognition task. This work provides a new strategy toward the implementation of all-hardware computing for convolutional neural networks.

Implementation of Multiply Accumulate Operation and Convolutional Neural Network Based on Ferroelectric Tunnel Junction Memristors

In the era of big data, traditional Von Neumann computers suffer from inefficiencies in terms of energy consumption and speed associated with data transfer between storage and processing. In-memory computing using ferroelectric tunnel junction (FTJ) memristors offers a potential solution to this challenge. Here, Hf0.5Zr0.5O2-based FTJs on a silicon substrate are fabricated, which demonstrates 32 conductance states (5-bit), low cycle-to-cycle variation (1.6%) and highly linear (nonlinearity <1) conductance manipulation. Based on an FTJ array with multiple FTJ devices, a custom-designed board with a field programmable gate array is utilized to perform accurate multiply accumulate operations and for image processing as various convolution operators. Notably, using FTJ devices as a convolutional layer, the convolutional neural network achieves a high accuracy of 92.5% for handwritten digit recognition, and exhibits orders of magnitude better energy efficiency compared to traditional CPU and GPU implementations. These findings highlight the promising potential of FTJs for realizing in-memory computing at the hardware level.

Interfacial Electronic Charge Trapping and Photonic Carrier Excitation Coupling in Solution-Processed Zinc-Tin Oxide Thin-Film Transistors Applied for Logic Gate Design and Quantized Neural Network

Components needed in Artificial Intelligence with a higher information capacity are critically needed and have garnered significant attention at the forefront of information technology. This study utilizes solution-processed zinc-tin oxide (ZTO) thin-film phototransistors and modulates the values of VG, which allows for the regulation of electron trapping/detrapping at the ZTO/SiO2 interface. By coupling the excited photonic carrier and electronic trapping, logic gates such as "AND," "OR," "NAND," and "NOR" can be achieved. With the exponential growth in data generation, efficient processing and storage solutions are imperative. However, extensive data transfer between computing units and storage limits the level of artificial neural networks (ANNs). Consequently, quantized neural networks (QNNs) have gained interest for their reduced computational resource requirements and lower consumption. In this context, we introduce an optimized ternary logic circuit based on ZTO devices. By utilizing optical modulation to adjust the turn-on voltage of the single device, we demonstrate the achievement of ternary current states, thereby providing three distinct discrete states. This configuration can be extended to QNN computing, demonstrating multilevel quantized current values for in-memory computation. We achieved a handwriting digit recognition rate of 91.6%, thereby demonstrating reliable QNN hardware performance. This robust QNN performance indicates that the metal oxide phototransistor shows significant potential for future ternary computing systems.

Two-dimensional material-based memristive devices for alternative computing

Two-dimensional (2D) materials have emerged as promising building blocks for next generation memristive devices, owing to their unique electronic, mechanical, and thermal properties, resulting in effective switching mechanisms for charge transport. Memristors are key components in a wide range of applications including neuromorphic computing, which is becoming increasingly important in artificial intelligence applications. Crossbar arrays are an important component in the development of hardware-based neural networks composed of 2D materials. In this paper, we summarize the current state of research on 2D material-based memristive devices utilizing different switching mechanisms, along with the application of these devices in neuromorphic crossbar arrays. Additionally, we discuss the challenges and future directions for the field.

New-Style Logic Operation and Neuromorphic Computing Enabled by Optoelectronic Artificial Synapses in an MXene/Y:HfO2 Ferroelectric Memristor

Today's computing systems, to meet the enormous demands of information processing, have driven the development of brain-inspired neuromorphic systems. However, there are relatively few optoelectronic devices in most brain-inspired neuromorphic systems that can simultaneously regulate the conductivity through both optical and electrical signals. In this work, the Au/MXene/Y:HfO2/FTO ferroelectric memristor as an optoelectronic artificial synaptic device exhibited both digital and analog resistance switching (RS) behaviors under different voltages with a good switching ratio (>103). Under optoelectronic conditions, optimal weight update parameters and an enhanced algorithm achieved 97.1% recognition accuracy in convolutional neural networks. A new logic gate circuit specifically designed for optoelectronic inputs was established. Furthermore, the device integrates the impact of relative humidity to develop an innovative three-person voting mechanism with a veto power. These results provide a feasible approach for integrating optoelectronic artificial synapses with logic-based computing devices.

Neuron Circuit Based on a Split-gate Transistor with Nonvolatile Memory for Homeostatic Functions of Biological Neurons

To mimic the homeostatic functionality of biological neurons, a split-gate field-effect transistor (S-G FET) with a charge trap layer is proposed within a neuron circuit. By adjusting the number of charges trapped in the Si3N4 layer, the threshold voltage (Vth) of the S-G FET changes. To prevent degradation of the gate dielectric due to program/erase pulses, the gates for read operation and Vth control were separated through the fin structure. A circuit that modulates the width and amplitude of the pulse was constructed to generate a Program/Erase pulse for the S-G FET as the output pulse of the neuron circuit. By adjusting the Vth of the neuron circuit, the firing rate can be lowered by increasing the Vth of the neuron circuit with a high firing rate. To verify the performance of the neural network based on S-G FET, a simulation of online unsupervised learning and classification in a 2-layer SNN is performed. The results show that the recognition rate was improved by 8% by increasing the threshold of the neuron circuit fired.

Programmable Threshold Logic Implementations in a Memristor Crossbar Array

In this study, we demonstrate the implementation of programmable threshold logics using a 32 × 32 memristor crossbar array. Thanks to forming-free characteristics obtained by the annealing process, its accurate programming characteristics are presented by a 256-level grayscale image. By simultaneous subtraction between weighted sum and threshold values with a differential pair in an opposite way, 3-input and 4-input Boolean logics are implemented in the crossbar without additional reference bias. Also, we verify a full-adder circuit and analyze its fidelity, depending on the device programming accuracy. Lastly, we successfully implement a 4-bit ripple carry adder in the crossbar and achieve reliable operations by read-based logic operations. Compared to stateful logic driven by device switching, a 4-bit ripple carry adder on a memristor crossbar array can perform more reliably in fewer steps thanks to its read-based parallel logic operation.