Algorithm and hardware considerations for real-time neural signal on-implant processing

Closed-Loop Deep Brain Stimulation Platform for Translational Research

OBJECTIVE

This study aims to facilitate the translation of innovative closed-loop deep brain stimulation (DBS) strategies from theory to practice by establishing a research platform. The platform addresses the challenges of real-time stimulation artifact removal, low-latency feedback stimulation, and rapid translation from animal to clinical experiments.

MATERIALS AND METHODS

The platform comprises hardware for neural sensing and stimulation, a closed-loop software framework for real-time data streaming and computation, and an algorithm library for implementing closed-loop DBS strategies. The platform integrates hardware for both animal and clinical research. The closed-loop software framework handles the entire closed-loop stimulation, including data streaming, stimulation artifact removal, preprocessing, a closed-loop stimulation strategy, and stimulation control. It provides a unified programming interface for both C/C++ and Python, enabling secondary development to integrate new closed-loop stimulation strategies. Additionally, the platform includes an algorithm library with signal processing and machine learning methods to facilitate the development of new closed-loop DBS strategies.

RESULTS

The platform can achieve low-latency feedback stimulation control with response times of 6.23 ± 0.85 ms and 6.95 ± 1.11 ms for animal and clinical experiments, respectively. It effectively removed stimulation artifacts and demonstrated flexibility in implementing new closed-loop DBS algorithms. The platform has integrated several typical closed-loop protocols, including threshold-adaptive DBS, amplitude-modulation DBS, dual-threshold DBS and neural state-dependent DBS.

CONCLUSIONS

This work provides a research tool for rapidly deploying innovative closed-loop strategies for translational research in both animal and clinical studies. The platform's capabilities in real-time data processing and low-latency control represent a significant advancement in translational DBS research, with potential implications for the development of more effective therapeutic interventions.

An active electronic, high-density epidural paddle array for chronic spinal cord neuromodulation

Objective. Epidural electrical stimulation (EES) has shown promise as both a clinical therapy and research tool for studying nervous system function. However, available clinical EES paddles are limited to using a small number of contacts due to the burden of wires necessary to connect each contact to the therapeutic delivery device, limiting the treatment area or density of epidural electrode arrays. We aimed to eliminate this burden using advanced on-paddle electronics.Approach. We developed a smart EES paddle with a 60-electrode programmable array, addressable using an active electronic multiplexer embedded within the electrode paddle body. The electronics are sealed in novel, ultra-low profile hermetic packaging. We conducted extensive reliability testing on the novel array, including a battery of ISO 10993-1 biocompatibility tests and determination of the hermetic package leak rate. We then evaluated the EES devicein vivo, placed on the epidural surface of the ovine lumbosacral spinal cord for 15 months.Main results.The active paddle array performed nominally when implanted in sheep for over 15 months and no device-related malfunctions were observed. The onboard multiplexer enabled bespoke electrode arrangements across, and within, experimental sessions. We identified stereotyped responses to stimulation in lower extremity musculature, and examined local field potential responses to EES using high-density recording bipoles. Finally, spatial electrode encoding enabled machine learning models to accurately perform EES parameter inference for unseen stimulation electrodes, reducing the need for extensive training data in future deep models.Significance. We report the development and chronic large animalin vivoevaluation of a high-density EES paddle array containing active electronics. Our results provide a foundation for more advanced computation and processing to be integrated directly into devices implanted at the neural interface, opening new avenues for the study of nervous system function and new therapies to treat neural injury and dysfunction.

A 0.53-μW/channel calibration-free spike detection IC with 98.8-%-accuracy based on stationary wavelet transforms and Teager energy operators

Objective. The brain-computer interface is currently experiencing a surge in the number of recording channels, resulting in a vast amount of raw data. It has become crucial to reliably detect neural spikes from a large population of neurons in the presence of noise, in order to constrain the transmission bandwidth.Approach. We investigate various time-frequency analysis methods for spike detection, followed by an exploration of energy operators amplifying spikes and signal statistics for adaptive thresholding. Subsequently, we introduce a precise and computationally efficient spike detection module, leveraging stationary wavelet transform (SWT), Teager energy operator, and root-mean-square calculator. This module is capable of autonomously adapting to different levels of noise. The SWT effectively eliminates high-frequency noise, enhancing the performance of the energy operators. The hardware computational process is simplified through the use of the lifting scheme and a channel-interleaving architecture.Main results. We evaluate the proposed spike detector with adaptive threshold on the publicly available WaveClus datasets. The detector achieves an average accuracy of 98.84%. The application-specific integrated circuit (ASIC) implementation results of the spike detector demonstrate an optimized interleaving channel of 8. In a 65 nm technology, the 8-channel spike detector consumes a power of 0.532μW Ch-1and occupies an area of 0.00645 mm2Ch-1, operating at a 1.2 V supply voltage.Significance. The proposed spike detection processor offers one of the highest accuracies among state-of-the-art spike detection methods. Importantly, the ASIC explores the considerations in the scalability and hardware costs. The proposed design provides a systematic solution on spike detection with adaptive thresholding, offering a high accuracy while maintaining low power and area consumptions.

Technical survey of end-to-end signal processing in BCIs using invasive MEAs

Modern brain-computer interfaces and neural implants allow interaction between the tissue, the user and the environment, where people suffer from neurodegenerative diseases or injuries.This interaction can be achieved by using penetrating/invasive microelectrodes for extracellular recordings and stimulation, such as Utah or Michigan arrays. The application-specific signal processing of the extracellular recording enables the detection of interactions and enables user interaction. For example, it allows to read out movement intentions from recordings of brain signals for controlling a prosthesis or an exoskeleton. To enable this, computationally complex algorithms are used in research that cannot be executed on-chip or on embedded systems. Therefore, an optimization of the end-to-end processing pipeline, from the signal condition on the electrode array over the analog pre-processing to spike-sorting and finally the neural decoding process, is necessary for hardware inference in order to enable a local signal processing in real-time and to enable a compact system for achieving a high comfort level. This paper presents a survey of system architectures and algorithms for end-to-end signal processing pipelines of neural activity on the hardware of such neural devices, including (i) on-chip signal pre-processing, (ii) spike-sorting on-chip or on embedded hardware and (iii) neural decoding on workstations. A particular focus for the hardware implementation is on low-power electronic design and artifact-robust algorithms with low computational effort and very short latency. For this, current challenges and possible solutions with support of novel machine learning techniques are presented in brief. In addition, we describe our future vision for next-generation BCIs.

Wearable and implantable biosensors: mechanisms and applications in closed-loop therapeutic systems

This review article examines the current state of wearable and implantable biosensors, offering an overview of their biosensing mechanisms and applications. We also delve into integrating these biosensors with therapeutic systems, discussing their operational principles and incorporation into closed-loop devices. Biosensing strategies are broadly categorized into chemical sensing for biomarker detection, physical sensing for monitoring physiological conditions such as pressure and temperature, and electrophysiological sensing for capturing bioelectrical activities. The discussion extends to recent developments in drug delivery and electrical stimulation devices to highlight their significant role in closed-loop therapy. By integrating with therapeutic devices, biosensors enable the modulation of treatment regimens based on real-time physiological data. This capability enhances the patient-specificity of medical interventions, an essential aspect of personalized healthcare. Recent innovations in integrating biosensors and therapeutic devices have led to the introduction of closed-loop wearable and implantable systems capable of achieving previously unattainable therapeutic outcomes. These technologies represent a significant leap towards dynamic, adaptive therapies that respond in real-time to patients' physiological states, offering a level of accuracy and effectiveness that is particularly beneficial for managing chronic conditions. This review also addresses the challenges associated with biosensor technologies. We also explore the prospects of these technologies to address their potential to transform disease management with more targeted and personalized treatment solutions.

Comparative analysis of energy transfer mechanisms for neural implants

As neural implant technologies advance rapidly, a nuanced understanding of their powering mechanisms becomes indispensable, especially given the long-term biocompatibility risks like oxidative stress and inflammation, which can be aggravated by recurrent surgeries, including battery replacements. This review delves into a comprehensive analysis, starting with biocompatibility considerations for both energy storage units and transfer methods. The review focuses on four main mechanisms for powering neural implants: Electromagnetic, Acoustic, Optical, and Direct Connection to the Body. Among these, Electromagnetic Methods include techniques such as Near-Field Communication (RF). Acoustic methods using high-frequency ultrasound offer advantages in power transmission efficiency and multi-node interrogation capabilities. Optical methods, although still in early development, show promising energy transmission efficiencies using Near-Infrared (NIR) light while avoiding electromagnetic interference. Direct connections, while efficient, pose substantial safety risks, including infection and micromotion disturbances within neural tissue. The review employs key metrics such as specific absorption rate (SAR) and energy transfer efficiency for a nuanced evaluation of these methods. It also discusses recent innovations like the Sectored-Multi Ring Ultrasonic Transducer (S-MRUT), Stentrode, and Neural Dust. Ultimately, this review aims to help researchers, clinicians, and engineers better understand the challenges of and potentially create new solutions for powering neural implants.

Calibration-Free and Hardware-Efficient Neural Spike Detection for Brain Machine Interfaces

Recent translational efforts in brain-machine interfaces (BMI) are demonstrating the potential to help people with neurological disorders. The current trend in BMI technology is to increase the number of recording channels to the thousands, resulting in the generation of vast amounts of raw data. This in turn places high bandwidth requirements for data transmission, which increases power consumption and thermal dissipation of implanted systems. On-implant compression and/or feature extraction are therefore becoming essential to limiting this increase in bandwidth, but add further power constraints - the power required for data reduction must remain less than the power saved through bandwidth reduction. Spike detection is a common feature extraction technique used for intracortical BMIs. In this article, we develop a novel firing-rate-based spike detection algorithm that requires no external training and is hardware efficient and therefore ideally suited for real-time applications. Key performance and implementation metrics such as detection accuracy, adaptability in chronic deployment, power consumption, area utilization, and channel scalability are benchmarked against existing methods using various datasets. The algorithm is first validated using a reconfigurable hardware (FPGA) platform and then ported to a digital ASIC implementation in both 65 nm and 0.18 μm CMOS technologies. The 128-channel ASIC design implemented in a 65 nm CMOS technology occupies 0.096 mm2 silicon area and consumes 4.86 μW from a 1.2 V power supply. The adaptive algorithm achieves a 96% spike detection accuracy on a commonly used synthetic dataset, without the need for any prior training.

Power-efficientin vivobrain-machine interfaces via brain-state estimation

Objective.Advances in brain-machine interfaces (BMIs) can potentially improve the quality of life of millions of users with spinal cord injury or other neurological disorders by allowing them to interact with the physical environment at their will.Approach.To reduce the power consumption of the brain-implanted interface, this article presents the first hardware realization of anin vivointention-aware interface via brain-state estimation.Main Results.It is shown that incorporating brain-state estimation reduces thein vivopower consumption and reduces total energy dissipation by over 1.8× compared to those of the current systems, enabling longer better life for implanted circuits. The synthesized application-specific integrated circuit (ASIC) of the designed intention-aware multi-unit spike detection system in a standard 180 nm CMOS process occupies 0.03 mm²of silicon area and consumes 0.63 µW of power per channel, which is the least power consumption among the currentin vivoASIC realizations.Significance.The proposed interface is the first practical approach towards realizing asynchronous BMIs while reducing the power consumption of the BMI interface and enhancing neural decoding performance compared to those of the conventional synchronous BMIs.