Time and rate dependent synaptic learning in neuro-mimicking resistive memories

Memristors have demonstrated immense potential as building blocks in future adaptive neuromorphic architectures. Recently, there has been focus on emulating specific synaptic functions of the mammalian nervous system by either tailoring the functional oxides or engineering the external programming hardware. However, high device-to-device variability in memristors induced by the electroforming process and complicated programming hardware are among the key challenges that hinder achieving biomimetic neuromorphic networks. Here, a simple hybrid complementary metal oxide semiconductor (CMOS)-memristor approach is reported to implement different synaptic learning rules by utilizing a CMOS-compatible memristor based on oxygen-deficient SrTiO3-x (STOx). The potential of such hybrid CMOS-memristor approach is demonstrated by successfully imitating time-dependent (pair and triplet spike-time-dependent-plasticity) and rate-dependent (Bienenstosk-Cooper-Munro) synaptic learning rules. Experimental results are benchmarked against in-vitro measurements from hippocampal and visual cortices with good agreement. The scalability of synaptic devices and their programming through a CMOS drive circuitry elaborates the potential of such an approach in realizing adaptive neuromorphic computation and networks.

Reproducible Performance Improvements to Monolayer MoS2 Transistors through Exposed Material Forming Gas Annealing

Metal-mediated exfoliation has been demonstrated as a promising approach for obtaining large-area flakes of two-dimensional (2D) materials to fabricate prototypical nanoelectronics. However, several processing challenges related to organic contamination at the interface of a 2D material and gate oxide must be overcome to realize robust devices with high yields. Here, we demonstrate an optimized process to realize high-performance field-effect transistor (FET) arrays from large-area (∼5000 μm²), monolayer MoS₂ with a yield of 85%. A central element of this process is an exposed material forming gas anneal (EM-FGA) that results in uniform FET performance metrics (i.e., field-effect mobilities, threshold voltages, and contact performance). Complementary analytical measurements show that the EM-FGA process reduces deleterious channel doping effects by decreasing organic contamination while also reducing the prevalence of insulating molybdenum oxide, effectively improving the MoS₂-gate oxide interface. The uniform FET performance metrics and high device yield achieved by applying the EM-FGA technique on large-area 2D material flakes will help advance the fabrication of complex 2D nanoelectronic devices and demonstrate the need for improved engineering of the 2D material-gate oxide interface.

Optically Stimulated Artificial Synapse Based on Layered Black Phosphorus

The translation of biological synapses onto a hardware platform is an important step toward the realization of brain-inspired electronics. However, to mimic biological synapses, devices till-date continue to rely on the need for simultaneously altering the polarity of an applied electric field or the output of these devices is photonic instead of an electrical synapse. As the next big step toward practical realization of optogenetics inspired circuits that exhibit fidelity and flexibility of biological synapses, optically-stimulated synaptic devices without a need to apply polarity-altering electric field are needed. Utilizing a unique photoresponse in black phosphorus (BP), here reported is an all-optical pathway to emulate excitatory and inhibitory action potentials by exploiting oxidation-related defects. These optical synapses are capable of imitating key neural functions such as psychological learning and forgetting, spatiotemporally correlated dynamic logic and Hebbian spike-time dependent plasticity. These functionalities are also demonstrated on a flexible platform suitable for wearable electronics. Such low-power consuming devices are highly attractive for deployment in neuromorphic architectures. The manifestation of cognition and spatiotemporal processing solely through optical stimuli provides an incredibly simple and powerful platform to emulate sophisticated neural functionalities such as associative sensory data processing and decision making.

Exchange-driven Magnetic Logic

Direct exchange interaction allows spins to be magnetically ordered. Additionally, it can be an efficient manipulation pathway for low-powered spintronic logic devices. We present a novel logic scheme driven by exchange between two distinct regions in a composite magnetic layer containing a bistable canted magnetization configuration. By applying a magnetic field pulse to the input region, the magnetization state is propagated to the output via spin-to-spin interaction in which the output state is given by the magnetization orientation of the output region. The dependence of this scheme with input field conditions is extensively studied through a wide range of micromagnetic simulations. These results allow different logic operating modes to be extracted from the simulation results, and majority logic is successfully demonstrated.

Nanoionics-Based Three-Terminal Synaptic Device Using Zinc Oxide

Artificial synaptic thin film transistors (TFTs) capable of simultaneously manifesting signal transmission and self-learning are demonstrated using transparent zinc oxide (ZnO) in combination with high κ tantalum oxide as gate insulator. The devices exhibit pronounced memory retention with a memory window in excess of 4 V realized using an operating voltage less than 6 V. Gate polarity induced motion of oxygen vacancies in the gate insulator is proposed to play a vital role in emulating synaptic behavior, directly measured as the transmission of a signal between the source and drain (S/D) terminals, but with the added benefit of independent control of synaptic weight. Unlike in two terminal memristor/resistive switching devices, multistate memory levels are demonstrated using the gate terminal without hampering the signal transmission across the S/D electrodes. Synaptic functions in the devices can be emulated using a low programming voltage of 200 mV, an order of magnitude smaller than in conventional resistive random access memory and other field effect transistor based synaptic technologies. Robust synaptic properties demonstrated using fully transparent, ecofriendly inorganic materials chosen here show greater promise in realizing scalable synaptic devices compared to organic synaptic and other liquid electrolyte gated device technologies. Most importantly, the strong coupling between the in-plane gate and semiconductor channel through ionic charge in the gate insulator shown by these devices, can lead to an artificial neural network with multiple presynaptic terminals for complex synaptic learning processes. This provides opportunities to alleviate the extreme requirements of component and interconnect density in realizing brainlike systems.

Ferroelectric memory based on nanostructures

In the past decades, ferroelectric materials have attracted wide attention due to their applications in nonvolatile memory devices (NVMDs) rendered by the electrically switchable spontaneous polarizations. Furthermore, the combination of ferroelectric and nanomaterials opens a new route to fabricating a nanoscale memory device with ultrahigh memory integration, which greatly eases the ever increasing scaling and economic challenges encountered in the traditional semiconductor industry. In this review, we summarize the recent development of the nonvolatile ferroelectric field effect transistor (FeFET) memory devices based on nanostructures. The operating principles of FeFET are introduced first, followed by the discussion of the real FeFET memory nanodevices based on oxide nanowires, nanoparticles, semiconductor nanotetrapods, carbon nanotubes, and graphene. Finally, we present the opportunities and challenges in nanomemory devices and our views on the future prospects of NVMDs.

Nanoscale memory devices

This article reviews the current status and future prospects for the use of nanomaterials and devices in memory technology. First, the status and continuing scaling trends of the flash memory are discussed. Then, a detailed discussion on technologies trying to replace flash in the near-term is provided. This includes phase change random access memory, Fe random access memory and magnetic random access memory. The long-term nanotechnology prospects for memory devices include carbon-nanotube-based memory, molecular electronics and memristors based on resistive materials such as TiO(2).

Electrical properties of Si-SiO(2)-Si nanogaps

The chances of attaching organic molecules to silicon surfaces can be considerably enhanced if a robust nanogap structure with silicon electrodes can be used to connect the molecules. We describe the electrical properties of such an electrode structure, with a separation of the silicon surfaces in the 3-7 nm range. These silicon nanogaps are manufactured by partly removing the silicon dioxide insulator from a silicon-oxide-silicon material stack, by using a selective oxide etchant. After the activation of the gap (the etching), current instabilities appear, which are comparable to the properties of thin oxides after soft breakdown. Applying a constant voltage can reduce these current instabilities. We also address the issue of surface leakage currents for these nanogap structures.

Scaling constraints in nanoelectronic random-access memories

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 x 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 x 512.