CMOS Ultrasound Transceiver Chip for High-Resolution Ultrasonic Imaging Systems

Design of Preamplifier for Ultrasound Transducers

In diagnostic ultrasound imaging applications, preamplifiers are used as first-stage analog front-end amplifiers for ultrasound transducers because they can amplify weak acoustic signals generated directly by ultrasound transducers. For emerging diagnostic ultrasound imaging applications, different types of preamplifiers with specific design parameters and circuit topologies have been developed, depending on the types of the ultrasound transducer. In particular, the design parameters of the preamplifier, such as the gain, bandwidth, input- or output-referred noise components, and power consumption, have a tradeoff relationship. Guidelines on the detailed design concept, design parameters, and specific circuit design techniques of the preamplifier used for ultrasound transducers are outlined in this paper, aiming to help circuit designers and academic researchers optimize the performance of ultrasound transducers used in the diagnostic ultrasound imaging applications for research directions.

Echo Signal Receiving and Data Conversion Integrated Circuits for Portable High-Frequency Ultrasonic Imaging System

Ultrasonic imaging has become a very promising technology, and it has been widely applied in biomedicine, geology, and other fields due to its advantages of safety, nondamaging, and real time. Especially, the portable high-frequency (>20 MHz) ultrasonic imaging system (UIS) has been generally used in biomedical detection and diagnosis. In the complex actual environment, the effect of integrated circuits (ICs) on the performance of portable high-frequency UIS is obvious. In the echo signal transmission link, the analog front end (AFE) and the analog-to-digital converter (ADC) are the two most critical modules, where AFE is used to receive and preprocess the analog ultrasonic echo signals and ADC to convert the analog signals from the AFE output to digital. The structure and performance of the ICs integrated into terminal equipment and in-probe for the portable high-frequency UIS are introduced and discussed. Some typical commercial ICs are also summarized. Based on the requirements and challenges of portable high-frequency UIS, the future development directions of ICs mainly include high integration, ultralow power consumption, high speed, and high precision, which can provide valuable reference and advice for the design of AFE and ADC for portable high-frequency UIS.

A Prototype System With Custom-Designed RX ICs for Contrast-Enhanced Ultrasound Imaging

This work presents a prototype system based on a multichannel receiving (RX) integrated circuit (IC) for contrast-enhanced ultrasound (CEUS) imaging. The RX IC is implemented in a 40-nm low-voltage CMOS technology and is designed to interface to a capacitive micromachined ultrasonic transducer array. To enable a direct connection of the RX electronics to the transducer, an analog multiplexer with on-chip protection circuitry is developed. Stress tests confirm the reliability of this arrangement when combined with a high-voltage pulser. The RX IC is equipped with a highly programmable bandpass filter to capture harmonic signals from ultrasound contrast agents (UCAs) while suppressing fundamental components. In order to examine the impact of analog front-end (AFE) bandpass filtering, in vitro acoustic experiments are performed with UCAs. A spatial resolution analysis suggests that the AFE bandpass filtering combined with a pulse inversion (PI) technique can improve the lateral resolution by 38% or 9% compared to the original full-bandwidth approach or a stand-alone PI approach, respectively, while the impact on axial resolution is negligible. A phantom study shows that compared to digital bandpass filtering, the AFE bandpass filtering enables better use of the dynamic range of the RX electronics, resulting in better generalized contrast-to-noise ratio from 0.44/0.53 to 0.57/0.68 without or with PI.

A Wideband Noise and Harmonic Distortion Canceling Low-Noise Amplifier for High-Frequency Ultrasound Transducers

This paper presents a wideband low-noise amplifier (LNA) front-end with noise and distortion cancellation for high-frequency ultrasound transducers. The LNA employs a resistive shunt-feedback structure with a feedforward noise-canceling technique to accomplish both wideband impedance matching and low noise performance. A complementary CMOS topology was also developed to cancel out the second-order harmonic distortion and enhance the amplifier linearity. A high-frequency ultrasound (HFUS) and photoacoustic (PA) imaging front-end, including the proposed LNA and a variable gain amplifier (VGA), was designed and fabricated in a 180 nm CMOS process. At 80 MHz, the front-end achieves an input-referred noise density of 1.36 nV/sqrt (Hz), an input return loss (S₁₁) of better than −16 dB, a voltage gain of 37 dB, and a total harmonic distortion (THD) of −55 dBc while dissipating a power of 37 mW, leading to a noise efficiency factor (NEF) of 2.66.

An RX AFE With Programmable BP Filter and Digitization for Ultrasound Harmonic Imaging

This paper presents a front-end integrated circuit for ultrasound (US) harmonic imaging, interfacing to a one-dimensional capacitive micromachined ultrasonic transducer (CMUT). It contains a complete ultrasound receiving chain, from analog front-end (AFE) to gigabit/s data link. A two-stage self-biased inverter-based transimpedance amplifier (TIA) is proposed in this work to improve tradeoffs between power, noise, and linearity at the first stage. To improve harmonic imaging performance, the design is further equipped with a 4[Formula: see text]-order highly programmable bandpass filter, which has a tunable bandwidth from 2 MHz to 15 MHz. An 8 b 80 MS/s SAR ADC digitizes the signal, which is further encoded and serialized into an LVDS data link, enabling a reduction in the number of output cables for future systems with multiple ADCs. The design is realized in a 40 nm CMOS technology. Electrical measurements show it consumes 2.9 mW for the AFE and 2.1 mW for the ADC and digital blocks. Its overall dynamic range varies from 61 dB to 69 dB, depending on the reception bandwidth. The imaging capability of this design is further demonstrated in a US transmission and reception imaging system. The acoustic measurements prove successful ultrasound harmonic acquisition, where the on-chip bandpass filter can improve the lateral resolution by more than 30%.

Multi-Channel Signal-Generator ASIC for Acoustic Holograms

A complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) has been developed to generate arbitrary, dynamic phase patterns for acoustic hologram applications. An experimental prototype has been fabricated to demonstrate phase shaping. It comprises a cascadable 1 ×9 array of identical, independently controlled signal generators implemented in a 0.35- [Formula: see text] minimum-feature-size process. It can individually control the phase of a square wave on each of the nine output pads. The footprint of the integrated circuit is [Formula: see text]. A 128-MHz clock frequency is used to produce outputs at 8 MHz with a phase resolution of 16 levels (4 bits) per channel. A 6 ×6 air-coupled matrix array ultrasonic transducer was built and driven by four ASICs, with the help of commercial buffer amplifiers, for the application demonstration. Acoustic pressure mapping and particle manipulation were performed. In addition, a 2 ×2 array piezoelectric micromachined ultrasonic transducer (PMUT) was connected and driven by four output channels of a single ASIC, demonstrating the flexibility of the ASIC to work with different transducers and the potential for direct integration of CMOS and PMUTs.

Quadrature Synthetic Aperture Beamforming Front-End for Miniaturized Ultrasound Imaging

A quadrature synthetic aperture front-end receiver for B-mode ultrasound imaging is presented. The receiver targets small-scale imaging applications such as capsule endoscopy and low-cost portable devices. System complexity, area, power consumption, and cost are minimized using synthetic aperture beamforming (SAB), whereby signals are processed in a sequential manner using only a single channel. SAB is combined with quadrature (I/Q) sampling, which further reduces the bandwidth and computational load. I/Q demodulation is carried out using a full custom analog front-end (AFE), which comprises a low-noise, variable gain preamplifier, followed by a passive mixer, programmable gain amplifier (PGA) and active lowpass filter. A novel preamplifier design is proposed, with quasi-exponential time-gain control and low noise (${\text{5.42 nV}}/\sqrt{\text{Hz}}$ input-referred noise). Overall, the AFE consumes ${\text{7.8 mW}}$ (static power) and occupies ${\text{1.5}}\,\text{mm}\times {\text{1.5}}\,\text{mm}$ in AMS ${\text{0.35}}\,\mu \text{m}$ CMOS. Real-time SAB is carried out using a Spartan-6 FPGA, which dynamically apodises and focuses the data by interpolating and applying complex phase rotations to the I/Q samples. For a frame rate of ${\text{7}}\,\text{Hz}$ , the power consumption is ${\text{3.4}}\,\text{mW}/\text{channel}$ across an aperture of 64 elements. B-mode images were obtained using a database of ultrasound signals ( ${\text{2.5}}\,\text{MHz}$ center frequency) derived from a commercial ultrasound machine. The normalized root mean squared error between the quadrature SAB image and the RF reference image was ${\text{13}}\%$. Image quality/frame rate may be tuned by varying the degree of spatial compounding.

Comparison of synthetic aperture architectures for miniaturised ultrasound imaging front-ends

Background

Point of care ultrasonography has been the focus of extensive research over the past few decades. Miniaturised, wireless systems have been envisaged for new application areas, such as capsule endoscopy, implantable ultrasound and wearable ultrasound. The hardware constraints of such small-scale systems are severe, and tradeoffs between power consumption, size, data bandwidth and cost must be carefully balanced.

Methods

In this work, two receiver architectures are proposed and compared to address these challenges. Both architectures uniquely combine low-rate sampling with synthetic aperture beamforming to reduce the data bandwidth and system complexity. The first architecture involves the use of quadrature sampling to minimise the signal bandwidth and computational load. Synthetic aperture beamforming (SAB) is carried out using a single-channel, pipelined protocol suitable for implementation on an FPGA/ASIC. The second architecture employs compressive sensing within the finite rate of innovation framework to further reduce the bandwidth. Low-rate signals are transmitted to a computational back-end (computer), which sequentially reconstructs each signal and carries out beamforming.

Results

Both architectures were tested using a custom hardware front-end and synthetic aperture database to yield B-mode images. The normalised root-mean-squared-error between the quadrature SAB image and the RF reference image was \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$13\%$$\end{document}13% while the compressive SAB error was \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$22\%$$\end{document}22% for the same degree of spatial compounding. The sampling rate is reduced by a factor of 2 (quadrature SAB) and 4.7 (compressive SAB), compared to the RF sampling rate. The quadrature method is implemented on FPGA, with a total power consumption of \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$4.1 $$\end{document}4.1 mW, which is comparable to state-of-the-art hardware topologies, but with significantly reduced circuit area.

Conclusions

Through a novel combination of SAB and low-rate sampling techniques, the proposed architectures achieve a significant reduction in data transmission rate, system complexity and digital/analogue circuit area. This allows for aggressive miniaturisation of the imaging front-end in portable imaging applications.

A Low-Power High-Dynamic-Range Receiver System for In-Probe 3-D Ultrasonic Imaging

In this paper, a dual-mode low-power, high dynamic-range receiver circuit is designed for the interface with a capacitive micromachined ultrasonic transducer. The proposed ultrasound receiver chip enables the development of an in-probe digital beamforming imaging system. The flexibility of having two operation modes offers a high dynamic range with minimum power sacrifice. A prototype of the chip containing one receive channel, with one variable transimpedance amplifier (TIA) and one analog to digital converter (ADC) circuit is implemented. Combining variable gain TIA functionality with ADC gain settings achieves an enhanced overall high dynamic range, while low power dissipation is maintained. The chip is designed and fabricated in a 65 nm standard CMOS process technology. The test chip occupies an area of 76[Formula: see text] 170 [Formula: see text]. A total average power range of 60-240 [Formula: see text] for a sampling frequency of 30 MHz, and a center frequency of 5 MHz is measured. An instantaneous dynamic range of 50.5 dB with an overall dynamic range of 72 dB is obtained from the receiver circuit.

Development of a Mechanical Scanning Device With High-Frequency Ultrasound Transducer for Ultrasonic Capsule Endoscopy

Wireless capsule endoscopy has opened a new era by enabling remote diagnostic assessment of the gastrointestinal tract in a painless procedure. Video capsule endoscopy is currently commercially available worldwide. However, it is limited to visualization of superficial tissue. Ultrasound (US) imaging is a complementary solution as it is capable of acquiring transmural information from the tissue wall. This paper presents a mechanical scanning device incorporating a high-frequency transducer specifically as a proof of concept for US capsule endoscopy (USCE), providing information that may usefully assist future research. A rotary solenoid-coil-based motor was employed to rotate the US transducer with sectional electronic control. A set of gears was used to convert the sectional rotation to circular rotation. A single-element focused US transducer with 39-MHz center frequency was used for high-resolution US imaging, connected to an imaging platform for pulse generation and image processing. Key parameters of US imaging for USCE applications were evaluated. Wire phantom imaging and tissue phantom imaging have been conducted to evaluate the performance of the proposed method. A porcine small intestine specimen was also used for imaging evaluation in vitro. Test results demonstrate that the proposed device and rotation mechanism are able to offer good image resolution ( [Formula: see text]) of the lumen wall, and they, therefore, offer a viable basis for the fabrication of a USCE device.

Low-Power Low-Noise Amplifier Using Attenuation-Adaptive Noise Control for Ultrasound Imaging Systems

This paper presents a low-noise amplifier (LNA) using attenuation-adaptive noise control (AANC) for ultrasound imaging systems. The proposed AANC reduces unnecessary power consumption of the LNA, which arises from useless noise floor, by controlling the noise floor of the LNA with respect to the attenuation of the ultrasound. In addition, a current feedback amplifier with a source-degenerated input stage reduces variations of the bandwidth and the closed loop gain, which are caused by the AANC. The proposed LNA was fabricated using a 0.18-[Formula: see text] CMOS process. The input-referred voltage noise density of the fabricated LNA is 1.01 [Formula: see text] at the frequency of 5 MHz. The second harmonic distortion is -53.5 dB when the input signal frequency is 5 MHz and the output voltage swing is 2 [Formula: see text]. The power consumption of the LNA using the AANC is 16.2 mW at the supply voltage of 1.8 V, which is reduced to 64% of that without using the AANC. The noise efficiency factor (NEF) of the proposed LNA is 3.69, to our knowledge, which is the lowest NEF compared with previous LNAs for ultrasound imaging.

A System-on-Chip Solution for Point-of-Care Ultrasound Imaging Systems: Architecture and ASIC Implementation

In this paper, we present a novel system-on-chip (SOC) solution for a portable ultrasound imaging system (PUS) for point-of-care applications. The PUS-SOC includes all of the signal processing modules (i.e., the transmit and dynamic receive beamformer modules, mid- and back-end processors, and color Doppler processors) as well as an efficient architecture for hardware-based imaging methods (e.g., dynamic delay calculation, multi-beamforming, and coded excitation and compression). The PUS-SOC was fabricated using a UMC 130-nm NAND process and has 16.8 GFLOPS of computing power with a total equivalent gate count of 12.1 million, which is comparable to a Pentium-4 CPU. The size and power consumption of the PUS-SOC are 27×27 mm(2) and 1.2 W, respectively. Based on the PUS-SOC, a prototype hand-held US imaging system was implemented. Phantom experiments demonstrated that the PUS-SOC can provide appropriate image quality for point-of-care applications with a compact PDA size ( 200×120×45 mm(3)) and 3 hours of battery life.

Class-DE Ultrasound Transducer Driver for HIFU Therapy

This paper presents a practical implementation of an integrated MRI-compatible CMOS amplifier capable of directly driving a piezoelectric ultrasound transducer suitable for high-intensity focused ultrasound (HIFU) therapy. The amplifier operates in Class DE mode without the need for an output matching network. The integrated amplifier has been implemented with the AMS AG H35 CMOS process. A class DE amplifier design methodology for driving unmatched piezoelectric loads is presented along with simulation and experimental results. The proposed design achieves approximately 90% efficiency with over 800 mW of output power at 1010 kHz. The total die area including pads is 2 mm(2). Compatibility with MRI was validated with B1 imaging of a phantom and the amplifier circuit.

A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging

One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

Development of integrated preamplifier for high-frequency ultrasonic transducers and low-power handheld receiver

This paper describes the design of a front-end circuit consisting of an integrated preamplifier with a Sallen-Key Butterworth filter for very-high-frequency ultrasonic transducers and a low-power handheld receiver. This preamplifier was fabricated using a 0.18-μm 7WL SiGe bi-polar complementary metal oxide semiconductor (BiCMOS) process. The Sallen-Key filter is used to increase the voltage gain of the front-end circuit for high-frequency transducers which are generally low in sensitivity. The measured peak voltage gain of the frontend circuits for the BiCMOS preamplifier with the Sallen-Key filter was 41.28 dB at 100 MHz with a-6-dB bandwidth of 91%, and the dc power consumption of the BiCMOS preamplifier was 49.53 mW. The peak voltage gain of the front-end circuits for the CMOS preamplifier with the Sallen-Key filter was 39.52 dB at 100 MHz with a-6-dB bandwidth of 108%, and the dc power consumption of the CMOS preamplifier was 43.57 mW. Pulse-echo responses and wire phantom images with a single-element ultrasonic transducer have been acquired to demonstrate the performance of the front-end circuit.