1
|
Fahimi Z, Mahmoodi MR, Nili H, Polishchuk V, Strukov DB. Combinatorial optimization by weight annealing in memristive hopfield networks. Sci Rep 2021; 11:16383. [PMID: 34385475 PMCID: PMC8361025 DOI: 10.1038/s41598-020-78944-5] [Citation(s) in RCA: 2] [Impact Index Per Article: 0.7] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 03/23/2020] [Accepted: 11/17/2020] [Indexed: 11/16/2022] Open
Abstract
The increasing utility of specialized circuits and growing applications of optimization call for the development of efficient hardware accelerator for solving optimization problems. Hopfield neural network is a promising approach for solving combinatorial optimization problems due to the recent demonstrations of efficient mixed-signal implementation based on emerging non-volatile memory devices. Such mixed-signal accelerators also enable very efficient implementation of various annealing techniques, which are essential for finding optimal solutions. Here we propose a “weight annealing” approach, whose main idea is to ease convergence to the global minima by keeping the network close to its ground state. This is achieved by initially setting all synaptic weights to zero, thus ensuring a quick transition of the Hopfield network to its trivial global minima state and then gradually introducing weights during the annealing process. The extensive numerical simulations show that our approach leads to a better, on average, solutions for several representative combinatorial problems compared to prior Hopfield neural network solvers with chaotic or stochastic annealing. As a proof of concept, a 13-node graph partitioning problem and a 7-node maximum-weight independent set problem are solved experimentally using mixed-signal circuits based on, correspondingly, a 20 × 20 analog-grade TiO2 memristive crossbar and a 12 × 10 eFlash memory array.
Collapse
Affiliation(s)
- Z Fahimi
- UC Santa Barbara, Santa Barbara, CA, 93106-9560, USA.
| | - M R Mahmoodi
- UC Santa Barbara, Santa Barbara, CA, 93106-9560, USA.
| | - H Nili
- UC Santa Barbara, Santa Barbara, CA, 93106-9560, USA
| | | | - D B Strukov
- UC Santa Barbara, Santa Barbara, CA, 93106-9560, USA
| |
Collapse
|
2
|
Berggren K, Xia Q, Likharev KK, Strukov DB, Jiang H, Mikolajick T, Querlioz D, Salinga M, Erickson JR, Pi S, Xiong F, Lin P, Li C, Chen Y, Xiong S, Hoskins BD, Daniels MW, Madhavan A, Liddle JA, McClelland JJ, Yang Y, Rupp J, Nonnenmann SS, Cheng KT, Gong N, Lastras-Montaño MA, Talin AA, Salleo A, Shastri BJ, de Lima TF, Prucnal P, Tait AN, Shen Y, Meng H, Roques-Carmes C, Cheng Z, Bhaskaran H, Jariwala D, Wang H, Shainline JM, Segall K, Yang JJ, Roy K, Datta S, Raychowdhury A. Roadmap on emerging hardware and technology for machine learning. Nanotechnology 2021; 32:012002. [PMID: 32679577 DOI: 10.1088/1361-6528/aba70f] [Citation(s) in RCA: 29] [Impact Index Per Article: 9.7] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/11/2023]
Abstract
Recent progress in artificial intelligence is largely attributed to the rapid development of machine learning, especially in the algorithm and neural network models. However, it is the performance of the hardware, in particular the energy efficiency of a computing system that sets the fundamental limit of the capability of machine learning. Data-centric computing requires a revolution in hardware systems, since traditional digital computers based on transistors and the von Neumann architecture were not purposely designed for neuromorphic computing. A hardware platform based on emerging devices and new architecture is the hope for future computing with dramatically improved throughput and energy efficiency. Building such a system, nevertheless, faces a number of challenges, ranging from materials selection, device optimization, circuit fabrication and system integration, to name a few. The aim of this Roadmap is to present a snapshot of emerging hardware technologies that are potentially beneficial for machine learning, providing the Nanotechnology readers with a perspective of challenges and opportunities in this burgeoning field.
Collapse
Affiliation(s)
- Karl Berggren
- Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA 02139, United States of America
| | - Qiangfei Xia
- Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, United States of America
| | | | - Dmitri B Strukov
- Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106, United States of America
| | - Hao Jiang
- School of Engineering & Applied Science Yale University, CT, United States of America
| | | | | | - Martin Salinga
- Institut für Materialphysik, Westfälische Wilhelms-Universität Münster, Germany
| | - John R Erickson
- Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA 15261, United States of America
| | - Shuang Pi
- Lam Research, Fremont, CA, United States of America
| | - Feng Xiong
- Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA 15261, United States of America
| | - Peng Lin
- Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA 02139, United States of America
| | - Can Li
- Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong SAR, China
| | - Yu Chen
- School of information science and technology, Fudan University, Shanghai, People's Republic of China
| | - Shisheng Xiong
- School of information science and technology, Fudan University, Shanghai, People's Republic of China
| | - Brian D Hoskins
- Physical Measurements Laboratory, National Institute of Standards and Technology, Gaithersburg, MD 20899, United States of America
| | - Matthew W Daniels
- Physical Measurements Laboratory, National Institute of Standards and Technology, Gaithersburg, MD 20899, United States of America
| | - Advait Madhavan
- Physical Measurements Laboratory, National Institute of Standards and Technology, Gaithersburg, MD 20899, United States of America
- Institute for Research in Electronics and Applied Physics, University of Maryland, College Park, MD, United States of America
| | - James A Liddle
- Physical Measurements Laboratory, National Institute of Standards and Technology, Gaithersburg, MD 20899, United States of America
| | - Jabez J McClelland
- Physical Measurements Laboratory, National Institute of Standards and Technology, Gaithersburg, MD 20899, United States of America
| | - Yuchao Yang
- School of Electronics Engineering and Computer Science, Peking University, Beijing, People's Republic of China
| | - Jennifer Rupp
- Department of Materials Science and Engineering and Department of Electrical Engineering & Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139, United States of America
- Electrochemical Materials, ETHZ Department of Materials, Hönggerbergring 64, Zürich 8093, Switzerland
| | - Stephen S Nonnenmann
- Department of Mechanical & Industrial Engineering, University of Massachusetts-Amherst, MA, United States of America
| | - Kwang-Ting Cheng
- School of Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong, People's Republic of China
| | - Nanbo Gong
- IBM T J Watson Research Center, Yorktown Heights, NY 10598, United States of America
| | - Miguel Angel Lastras-Montaño
- Instituto de Investigación en Comunicación Óptica, Facultad de Ciencias, Universidad Autónoma de San Luis Potosí, México
| | - A Alec Talin
- Sandia National Laboratories, Livermore, CA 94551, United States of America
| | - Alberto Salleo
- Department of Materials Science and Engineering, Stanford University, Stanford, California, United States of America
| | - Bhavin J Shastri
- Department of Physics, Engineering Physics & Astronomy, Queen's University, Kingston ON KL7 3N6, Canada
| | - Thomas Ferreira de Lima
- Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, United States of America
| | - Paul Prucnal
- Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, United States of America
| | - Alexander N Tait
- Physical Measurement Laboratory, National Institute of Standards and Technology (NIST), Boulder, CO 80305, United States of America
| | - Yichen Shen
- Lightelligence, 268 Summer Street, Boston, MA 02210, United States of America
| | - Huaiyu Meng
- Lightelligence, 268 Summer Street, Boston, MA 02210, United States of America
| | - Charles Roques-Carmes
- Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA 02139, United States of America
| | - Zengguang Cheng
- Department of Materials, University of Oxford, Oxford OX1 3PH, United Kingdom
- State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People's Republic of China
| | - Harish Bhaskaran
- Department of Materials, University of Oxford, Oxford OX1 3PH, United Kingdom
| | - Deep Jariwala
- Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia PA 19104, United States of America
| | - Han Wang
- University of Southern California, Los Angeles, CA 90089, United States of America
| | - Jeffrey M Shainline
- Physical Measurement Laboratory, National Institute of Standards and Technology (NIST), Boulder, CO 80305, United States of America
| | - Kenneth Segall
- Department of Physics and Astronomy, Colgate University, NY 13346, United States of America
| | - J Joshua Yang
- Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, United States of America
| | - Kaushik Roy
- School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, United States of America
| | - Suman Datta
- University of Notre Dame, Notre Dame, IN 46556, United States of America
| | - Arijit Raychowdhury
- Georgia Institute of Technology, Atlanta, GA 30332, United States of America
| |
Collapse
|
3
|
Merrikh-Bayat F, Guo X, Klachko M, Prezioso M, Likharev KK, Strukov DB. High-Performance Mixed-Signal Neurocomputing With Nanoscale Floating-Gate Memory Cell Arrays. IEEE Trans Neural Netw Learn Syst 2018; 29:4782-4790. [PMID: 29990267 DOI: 10.1109/tnnls.2017.2778940] [Citation(s) in RCA: 35] [Impact Index Per Article: 5.8] [Reference Citation Analysis] [What about the content of this article? (0)] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/08/2023]
Abstract
Potential advantages of analog- and mixed-signal nanoelectronic circuits, based on floating-gate devices with adjustable conductance, for neuromorphic computing had been realized long time ago. However, practical realizations of this approach suffered from using rudimentary floating-gate cells of relatively large area. Here, we report a prototype $28\times28$ binary-input, ten-output, three-layer neuromorphic network based on arrays of highly optimized embedded nonvolatile floating-gate cells, redesigned from a commercial 180-nm nor flash memory. All active blocks of the circuit, including 101 780 floating-gate cells, have a total area below 1 mm2. The network has shown a 94.7% classification fidelity on the common Modified National Institute of Standards and Technology benchmark, close to the 96.2% obtained in simulation. The classification of one pattern takes a sub-1- $\mu \text{s}$ time and a sub-20-nJ energy-both numbers much better than in the best reported digital implementations of the same task. Estimates show that a straightforward optimization of the hardware and its transfer to the already available 55-nm technology may increase this advantage to more than $10^{2}\times $ in speed and $10^{4}\times $ in energy efficiency.
Collapse
|
4
|
Affiliation(s)
- Dmitri B Strukov
- Department of Electrical and Computer Engineering, University of California Santa Barbara, Santa Barbara, CA, USA.
| |
Collapse
|
5
|
Hoskins BD, Adam GC, Strelcov E, Zhitenev N, Kolmakov A, Strukov DB, McClelland JJ. Stateful characterization of resistive switching TiO 2 with electron beam induced currents. Nat Commun 2017; 8:1972. [PMID: 29215006 PMCID: PMC5719452 DOI: 10.1038/s41467-017-02116-9] [Citation(s) in RCA: 24] [Impact Index Per Article: 3.4] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 04/28/2017] [Accepted: 11/08/2017] [Indexed: 11/23/2022] Open
Abstract
Metal oxide resistive switches are increasingly important as possible artificial synapses in next-generation neuromorphic networks. Nevertheless, there is still no codified set of tools for studying properties of the devices. To this end, we demonstrate electron beam-induced current measurements as a powerful method to monitor the development of local resistive switching in TiO2-based devices. By comparing beam energy-dependent electron beam-induced currents with Monte Carlo simulations of the energy absorption in different device layers, it is possible to deconstruct the origins of filament image formation and relate this to both morphological changes and the state of the switch. By clarifying the contrast mechanisms in electron beam-induced current microscopy, it is possible to gain new insights into the scaling of the resistive switching phenomenon and observe the formation of a current leakage region around the switching filament. Additionally, analysis of symmetric device structures reveals propagating polarization domains. Oxide-based memristors hold promise for artificial neuromorphic computing, yet the detail of the switching mechanism—filament formation—remains largely unknown. Hoskins et al. provide nanoscale imaging of this process using electron beam induced current microscopy and relate it to resistive states.
Collapse
Affiliation(s)
- Brian D Hoskins
- Center for Nanoscale Science and Technology, National Institute of Standards and Technology, Gaithersburg, MD, 20899, USA. .,Materials Department, University of California Santa Barbara, Santa Barbara, CA, 93106, USA.
| | - Gina C Adam
- Electrical and Computer Engineering Department, University of California Santa Barbara, Santa Barbara, CA, 93106, USA.,Institute for Research and Development in Microtechnologies, 077190, Bucharest, Romania
| | - Evgheni Strelcov
- Center for Nanoscale Science and Technology, National Institute of Standards and Technology, Gaithersburg, MD, 20899, USA.,Institute for Research in Electronics and Applied Physics, University of Maryland, College Park, MD, 20742, USA
| | - Nikolai Zhitenev
- Center for Nanoscale Science and Technology, National Institute of Standards and Technology, Gaithersburg, MD, 20899, USA
| | - Andrei Kolmakov
- Center for Nanoscale Science and Technology, National Institute of Standards and Technology, Gaithersburg, MD, 20899, USA
| | - Dmitri B Strukov
- Electrical and Computer Engineering Department, University of California Santa Barbara, Santa Barbara, CA, 93106, USA
| | - Jabez J McClelland
- Center for Nanoscale Science and Technology, National Institute of Standards and Technology, Gaithersburg, MD, 20899, USA
| |
Collapse
|
6
|
Chakrabarti B, Lastras-Montaño MA, Adam G, Prezioso M, Hoskins B, Payvand M, Madhavan A, Ghofrani A, Theogarajan L, Cheng KT, Strukov DB. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit. Sci Rep 2017; 7:42429. [PMID: 28195239 PMCID: PMC5307953 DOI: 10.1038/srep42429] [Citation(s) in RCA: 47] [Impact Index Per Article: 6.7] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 09/30/2016] [Accepted: 01/09/2017] [Indexed: 11/24/2022] Open
Abstract
Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.
Collapse
Affiliation(s)
- B Chakrabarti
- Electrical and Computer Engineering Department, University of California, Santa Barbara, CA, 93106, USA
| | - M A Lastras-Montaño
- Electrical and Computer Engineering Department, University of California, Santa Barbara, CA, 93106, USA
| | - G Adam
- Electrical and Computer Engineering Department, University of California, Santa Barbara, CA, 93106, USA
| | - M Prezioso
- Electrical and Computer Engineering Department, University of California, Santa Barbara, CA, 93106, USA
| | - B Hoskins
- Materials Department, University of California, Santa Barbara, CA, 93106, USA
| | | | | | | | | | - K-T Cheng
- Electrical and Computer Engineering Department, University of California, Santa Barbara, CA, 93106, USA.,School of Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
| | - D B Strukov
- Electrical and Computer Engineering Department, University of California, Santa Barbara, CA, 93106, USA
| |
Collapse
|
7
|
Guo X, Merrikh-Bayat F, Gao L, Hoskins BD, Alibart F, Linares-Barranco B, Theogarajan L, Teuscher C, Strukov DB. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits. Front Neurosci 2015; 9:488. [PMID: 26732664 PMCID: PMC4689862 DOI: 10.3389/fnins.2015.00488] [Citation(s) in RCA: 40] [Impact Index Per Article: 4.4] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Key Words] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 10/20/2015] [Accepted: 12/07/2015] [Indexed: 11/17/2022] Open
Abstract
The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2- x /Pt memristors and CMOS integrated circuit components.
Collapse
Affiliation(s)
- Xinjie Guo
- Department of Electrical and Computer Engineering, University of California, Santa BarbaraSanta Barbara, CA, USA
| | - Farnood Merrikh-Bayat
- Department of Electrical and Computer Engineering, University of California, Santa BarbaraSanta Barbara, CA, USA
| | - Ligang Gao
- Department of Electrical and Computer Engineering, University of California, Santa BarbaraSanta Barbara, CA, USA
| | - Brian D. Hoskins
- Department of Electrical and Computer Engineering, University of California, Santa BarbaraSanta Barbara, CA, USA
| | - Fabien Alibart
- Centre National de la Recherche ScientifiqueLille, France
| | - Bernabe Linares-Barranco
- Instituto de Microelectronica de Sevilla (Consejo Superior de Investigaciones Científicas and University of Seville)Seville, Spain
| | - Luke Theogarajan
- Department of Electrical and Computer Engineering, University of California, Santa BarbaraSanta Barbara, CA, USA
| | - Christof Teuscher
- Department of Electrical and Computer Engineering, Portland State UniversityPortland, OR, USA
| | - Dmitri B. Strukov
- Department of Electrical and Computer Engineering, University of California, Santa BarbaraSanta Barbara, CA, USA
| |
Collapse
|
8
|
Abstract
Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.
Collapse
Affiliation(s)
- J Joshua Yang
- Hewlett-Packard Laboratories, Palo Alto, California 94304, USA.
| | | | | |
Collapse
|
9
|
Alibart F, Gao L, Hoskins BD, Strukov DB. High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology 2012; 23:075201. [PMID: 22260949 DOI: 10.1088/0957-4484/23/7/075201] [Citation(s) in RCA: 49] [Impact Index Per Article: 4.1] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 05/31/2023]
Abstract
Using memristive properties common for titanium dioxide thin film devices, we designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to seven-bit precision) within its dynamic range even in the presence of large variations in switching behavior. The high precision state is nonvolatile and the results are likely to be sustained for nanoscale memristive devices because of the inherent filamentary nature of the resistive switching. The proposed functionality of memristive devices is especially attractive for analog computing with low precision data. As one representative example we demonstrate hybrid circuitry consisting of an integrated circuit summing amplifier and two memristive devices to perform the analog multiply-and-add (dot-product) computation, which is a typical bottleneck operation in information processing.
Collapse
Affiliation(s)
- Fabien Alibart
- Department of Electrical and Computer Engineering, University of California Santa Barbara, Santa Barbara, CA 93106, USA.
| | | | | | | |
Collapse
|
10
|
Strachan JP, Strukov DB, Borghetti J, Yang JJ, Medeiros-Ribeiro G, Williams RS. The switching location of a bipolar memristor: chemical, thermal and structural mapping. Nanotechnology 2011; 22:254015. [PMID: 21572186 DOI: 10.1088/0957-4484/22/25/254015] [Citation(s) in RCA: 5] [Impact Index Per Article: 0.4] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 05/10/2023]
Abstract
Memristors are memory resistors promising a rapid integration into future memory technologies. However, progress is still critically limited by a lack of understanding of the physical processes occurring at the nanoscale. Here we correlate device electrical characteristics with local atomic structure, chemistry and temperature. We resolved a single conducting channel that is made up of a reduced phase of the as-deposited titanium oxide. Moreover, we observed sufficient Joule heating to induce a crystallization of the oxide surrounding the channel, with a peculiar pattern that finite element simulations correlated with the existence of a hot spot close to the bottom electrode, thus identifying the switching location. This work reports direct observations in all three dimensions of the internal structure of titanium oxide memristors.
Collapse
Affiliation(s)
- John Paul Strachan
- Nanoelectronic Research Group, Hewlett-Packard Labs, Palo Alto, CA 94304, USA
| | | | | | | | | | | |
Collapse
|
11
|
Xia Q, Robinett W, Cumbie MW, Banerjee N, Cardinali TJ, Yang JJ, Wu W, Li X, Tong WM, Strukov DB, Snider GS, Medeiros-Ribeiro G, Williams RS. Memristor-CMOS hybrid integrated circuits for reconfigurable logic. Nano Lett 2009; 9:3640-5. [PMID: 19722537 DOI: 10.1021/nl901874j] [Citation(s) in RCA: 121] [Impact Index Per Article: 8.1] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 05/24/2023]
Abstract
Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.
Collapse
Affiliation(s)
- Qiangfei Xia
- Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, California 94304, USA.
| | | | | | | | | | | | | | | | | | | | | | | | | |
Collapse
|
12
|
|
13
|
Abstract
The memristor, the fourth passive circuit element, was predicted theoretically nearly 40 years ago, but we just recently demonstrated both an intentional material system and an analytical model that exhibited the properties of such a device. Here we provide a more physical model based on numerical solutions of coupled drift-diffusion equations for electrons and ions with appropriate boundary conditions. We simulate the dynamics of a two-terminal memristive device based on a semiconductor thin film with mobile dopants that are partially compensated by a small amount of immobile acceptors. We examine the mobile ion distributions, zero-bias potentials, and current-voltage characteristics of the model for both steady-state bias conditions and for dynamical switching to obtain physical insight into the transport processes responsible for memristive behavior in semiconductor films.
Collapse
|
14
|
|
15
|
Strukov DB, Likharev KK. Defect-tolerant architectures for nanoelectronic crossbar memories. J Nanosci Nanotechnol 2007; 7:151-67. [PMID: 17455481] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [MESH Headings] [Subscribe] [Scholar Register] [Indexed: 05/15/2023]
Abstract
We have calculated the maximum useful bit density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective crossbar nanoelectronic memories, as a function of defective memory cell fraction. While our calculations are based on a particular ("CMOL") memory topology, with naturally segmented nanowires and an area-distributed nano/CMOS interface, for realistic parameters our results are also applicable to "global" crossbar memories with peripheral interfaces. The results indicate that the crossbar memories with a nano/CMOS pitch ratio close to 1/3 (which is typical for the current, initial stage of the nanoelectronics development) may overcome purely semiconductor memories in useful bit density if the fraction of nanodevice defects (stuck-on-faults) is below approximately 15%, even under rather tough, 30 ns upper bound on the total access time. Moreover, as the technology matures, and the pitch ratio approaches an order of magnitude, the crossbar memories may be far superior to the densest semiconductor memories by providing, e.g., a 1 Tbit/cm2 density even for a plausible defect fraction of 2%. These highly encouraging results are much better than those reported in literature earlier, including our own early work, mostly due to more advanced error correcting codes.
Collapse
|