Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors

The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter's own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of -3.3 V.

A Multi-Dimensional Calibration Based on Genetic Algorithm in a 12-Bit 750 MS/s Pipelined ADC

As the preferred architecture for high-speed and high-resolution analog-to-digital converters (ADC), the accuracy of pipelined ADC is limited mainly by various errors arising from multiple digital-to-analog converters (MDAC). This paper presents a multi-dimensional (M-D) MDAC calibration based on a genetic algorithm (GA) in a 12-bit 750 MS/s pipelined ADC. The proposed M-D MDAC compensation model enables capacitor mismatch and static interstage gain error (IGE) compensation on the chip and prepares for subsequent background calibration based on a pseudo-random number (PN) injection to achieve accurate compensation for dynamic IGE. An M-D coefficient extraction scheme based on GA is also proposed to extract the required compensation coefficients of the foreground calibration, which avoids falling into local traps through MATLAB. The above calibration scheme has been verified in a prototype 12-bit 750 MS/s pipelined ADC. The measurement results show that the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are increased from 49.9 dB/66.7 dB to 59.6 dB/77.5 dB with the proposed calibration at 25 °C. With the help of background calibration at 85 °C, the SNDR and SFDR are improved by 3.4 dB and 8.8 dB, respectively.

An AC-Coupled 1st-order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this paper, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range and electrode DC offset cancellation. An AC-coupled 1st-order digitally-intensive Δ - Δ Σ architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits and a digital control, has been fabricated in 22-nm FDSOI CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 μ W , and an input-referred noise of 7.7 ± 0.4 μ V rms in the AP band and 11.9 ± 1.1 μ V rms in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

A 12-b Subranging SAR ADC Using Detect-and-Skip Switching and Mismatch Calibration for Biopotential Sensing Applications

This paper presents a 12-b successive approximation register (SAR) analog-to-digital converter (ADC) for biopotential sensing applications. To reduce the digital-to-analog converter (DAC) switching energy of the high-resolution ADC, we combine merged-capacitor-switching (MCS) and detect-and-skip (DAS) methods, successfully embedded in the subranging structure. The proposed method saves 96.7% of switching energy compared to the conventional method. Without an extra burden on the realization of the calibration circuit, we achieve mismatch calibration by reusing the on-chip DAC. The mismatch data are processed in the digital domain to compensate for the nonlinearity caused by the DAC mismatch. The ADC is realized using a 0.18 μm CMOS process with a core area of 0.7 mm². At the sampling rate f_S = 9 kS/s, the ADC achieves a signal-to-noise ratio and distortion (SINAD) of 67.4 dB. The proposed calibration technique improves the spurious-free dynamic range (SFDR) by 7.2 dB, resulting in 73.5 dB. At an increased f_S = 200 kS/s, the ADC achieves a SINAD of 65.9 dB and an SFDR of 68.8 dB with a figure-of-merit (FoM) of 13.2 fJ/conversion-step.

Information Conversion in Measuring Channels with Optoelectronic Sensors

The purpose of this work is the authors' attempt to identify the main phases of information transformation in measurement channels on the example of an optical measurement channel with microprocessor control. The authors include such phases: hardware implementation and analytical representation of an optical sensor's converting functions and a current-to-voltage converter; based on the methods of experimental computer science, the converting functions and sensitivity are deduced, analytical dependences for estimation of a range of measurement are obtained. It is shown that the choice of information transmission type in the microprocessor measuring channel significantly affects the speed of the measuring channel. Based on the uncertainty in the form of entropy before and after measurements, the amount of information for measuring channels with optoelectronic sensors is estimated. The application of the results obtained in the work allows even at the design stage of physical and mathematical modeling to assess the basic static metrological characteristics of measuring channels, aimed at reducing the stage of development and debugging of hardware and software and standardization of their metrological characteristics.

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm². At the sampling rate f_S = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at f_S = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.

Action spectra of photosystems II and I and quantum yield of photosynthesis in leaves in State 1

The spectral global quantum yield (YII, electrons/photons absorbed) of photosystem II (PSII) was measured in sunflower leaves in State 1 using monochromatic light. The global quantum yield of PSI (YI) was measured using low-intensity monochromatic light flashes and the associated transmittance change at 810nm. The 810-nm signal change was calibrated based on the number of electrons generated by PSII during the flash (4·O2 evolution) which arrived at the PSI donor side after a delay of 2ms. The intrinsic quantum yield of PSI (yI, electrons per photon absorbed by PSI) was measured at 712nm, where photon absorption by PSII was small. The results were used to resolve the individual spectra of the excitation partitioning coefficients between PSI (aI) and PSII (aII) in leaves. For comparison, pigment-protein complexes for PSII and PSI were isolated, separated by sucrose density ultracentrifugation, and their optical density was measured. A good correlation was obtained for the spectral excitation partitioning coefficients measured by these different methods. The intrinsic yield of PSI was high (yI=0.88), but it absorbed only about 1/3 of quanta; consequently, about 2/3 of quanta were absorbed by PSII, but processed with the low intrinsic yield yII=0.63. In PSII, the quantum yield of charge separation was 0.89 as detected by variable fluorescence Fv/Fm, but 29% of separated charges recombined (Laisk A, Eichelmann H and Oja V, Photosynth. Res. 113, 145-155). At wavelengths less than 580nm about 30% of excitation is absorbed by pigments poorly connected to either photosystem, most likely carotenoids bound in pigment-protein complexes.