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Zhao P, Cao L, Wang G, Wu Z, Yin H. The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks. Nanomaterials (Basel) 2023; 13:2971. [PMID: 37999325 PMCID: PMC10675435 DOI: 10.3390/nano13222971] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [What about the content of this article? (0)] [Affiliation(s)] [Abstract] [Key Words] [Grants] [Track Full Text] [Subscribe] [Scholar Register] [Received: 10/22/2023] [Revised: 11/04/2023] [Accepted: 11/13/2023] [Indexed: 11/25/2023]
Abstract
With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature (Tamb) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (Nstack) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different Tamb ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the Nstack increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (VZTC) decreases significantly in p-type nanoscale devices when Tamb is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different Nstacks are investigated at various Tambs. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of Tamb on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications.
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Affiliation(s)
- Peng Zhao
- Integrated Circuit Advanced Process R&D Center, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China; (P.Z.); (L.C.); (Z.W.)
- State Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
- School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China
| | - Lei Cao
- Integrated Circuit Advanced Process R&D Center, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China; (P.Z.); (L.C.); (Z.W.)
- State Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
- School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China
| | - Guilei Wang
- Process Integration, Beijing Superstring Academy of Memory Technology, Beijing 100176, China;
| | - Zhenhua Wu
- Integrated Circuit Advanced Process R&D Center, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China; (P.Z.); (L.C.); (Z.W.)
- State Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
- School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China
| | - Huaxiang Yin
- Integrated Circuit Advanced Process R&D Center, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China; (P.Z.); (L.C.); (Z.W.)
- State Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
- School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China
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