Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers

In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes.

The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks

With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature (Tamb) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (Nstack) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different Tamb ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the Nstack increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (VZTC) decreases significantly in p-type nanoscale devices when Tamb is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different Nstacks are investigated at various Tambs. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of Tamb on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications.

A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET)

The complementary field-effect transistor (CFET) with N-type FET (NFET) stacked on P-type FET (PFET) is a promising device structure based on gate-all-around FET (GAAFET). Because of the high-density stacked structure, the self-heating effect (SHE) becomes more and more severe. Buried thermal rail (BTR) technology on top of the buried power rail (BPR) process is proposed to improve heat dissipation. Through a systematical 3D Technology Computer Aided Design (TCAD) simulation, compared to traditional CFET and CFET with BPR only, the thermal resistance (Rth) of CFET can be significantly reduced with BTR technology, while the drive capability is also improved. Furthermore, based on the proposed BTR technology, different power delivery structures of top-VDD-top-VSS (TDTS), bottom-VDD-bottom-VSS (BDBS), and bottom-VDD-top-VSS (BDTS) were investigated in terms of electrothermal and parasitic characteristics. The Rth of the BTR-BDTS structure is decreased by 5% for NFET and 9% for PFET, and the Ion is increased by 2% for NFET and 7% for PFET.

Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO2/Si3N4 Dual-Layer Insulator

The self-heating effects (SHEs) on the electrical characteristics of the GaN MOSFETs with a stacked TiO₂/Si₃N₄ dual-layer insulator are investigated by using rigorous TCAD simulations. To accurately analyze them, the GaN MOSFETs with Si₃N₄ single-layer insulator are conducted to the simulation works together. The stacked TiO₂/Si₃N₄ GaN MOSFET has a maximum on-state current of 743.8 mA/mm, which is the improved value due to the larger oxide capacitance of TiO₂/Si₃N₄ than that of a Si₃N₄ single-layer insulator. However, the electrical field and current density increased by the stacked TiO₂/Si₃N₄ layers make the device’s temperature higher. That results in the degradation of the device’s performance. We simulated and analyzed the operation mechanisms of the GaN MOSFETs modulated by the SHEs in view of high-power and high-frequency characteristics. The maximum temperature inside the device was increased to 409.89 K by the SHEs. In this case, the stacked TiO₂/Si₃N₄-based GaN MOSFETs had 25%-lower values for both the maximum on-state current and the maximum transconductance compared with the device where SHEs did not occur; R_on increased from 1.41 mΩ·cm² to 2.56 mΩ·cm², and the cut-off frequency was reduced by 26% from 5.45 GHz. Although the performance of the stacked TiO₂/Si₃N₄-based GaN MOSFET is degraded by SHEs, it shows superior electrical performance than GaN MOSFETs with Si₃N₄ single-layer insulator.