A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications

Ratio-based multi-level resistive memory cells

Ratio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$x^2$$\end{document}x2 at the best case and \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$x^{\sqrt{2}}$$\end{document}x2 at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell’s programming time and programming energy by up 5–10\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}×, while achieving the same bit error probability.

Spontaneous sparse learning for PCM-based memristor neural networks

Neural networks trained by backpropagation have achieved tremendous successes on numerous intelligent tasks. However, naïve gradient-based training and updating methods on memristors impede applications due to intrinsic material properties. Here, we built a 39 nm 1 Gb phase change memory (PCM) memristor array and quantified the unique resistance drift effect. On this basis, spontaneous sparse learning (SSL) scheme that leverages the resistance drift to improve PCM-based memristor network training is developed. During training, SSL regards the drift effect as spontaneous consistency-based distillation process that reinforces the array weights at the high-resistance state continuously unless the gradient-based method switches them to low resistance. Experiments show that the SSL not only helps the convergence of network with better performance and sparsity controllability without additional computation in handwritten digit classification. This work promotes the learning algorithms with the intrinsic properties of memristor devices, opening a new direction for development of neuromorphic computing chips.

Picosecond multilevel resistive switching in tantalum oxide thin films

The increasing demand for high-density data storage leads to an increasing interest in novel memory concepts with high scalability and the opportunity of storing multiple bits in one cell. A promising candidate is the redox-based resistive switch repositing the information in form of different resistance states. For reliable programming, the underlying physical parameters need to be understood. We reveal that the programmable resistance states are linked to internal series resistances and the fundamental nonlinear switching kinetics. The switching kinetics of [Formula: see text]-based cells was investigated in a wide range over 15 orders of magnitude from 10[Formula: see text] s to 250 ps. The capacitive charging time of our device limits the direct observation of the set time below 770 ps, however, we found indication for an intrinsic switching speed of 10 ps at a stimulus of 3 V. On all time scales, multi-bit data storage capabilities were demonstrated. The elucidated link between fundamental material properties and multi-bit data storage paves the way for designing resistive switches for memory and neuromorphic applications.

Lead-Free Dual-Phase Halide Perovskites for Preconditioned Conducting-Bridge Memory

Organometallic and all-inorganic halide perovskites (HPs) have recently emerged as promising candidate materials for resistive switching (RS) nonvolatile memory due to their current-voltage hysteresis caused by fast ion migration. Lead-free and all-inorganic HPs have been researched for non-toxic and environmentally friendly RS memory devices. However, only HP-based devices with electrochemically active top electrode (TE) exhibit ultra-low operating voltages and high on/off ratio RS properties. The active TE easily reacts to halide ions in HP films, and the devices have a low device durability. Herein, RS memory devices based on an air-stable lead-free all-inorganic dual-phase HP (AgBi₂ I₇ -Cs₃ Bi₂ I₉ ) are successfully fabricated with inert metal electrodes. The devices with Au TE show filamentary RS behavior by conducting-bridge involving Ag cations in HPs with ultra-low operating voltages (<0.15 V), high on/off ratio (>10⁷ ), multilevel data storage, and long retention times (>5 × 10⁴ s). The use of a closed-loop pulse switching method improves reversible RS properties up to 10³ cycles with high on/off ratio above 10⁶ . With an extremely small bending radius of 1 mm, the devices are operable with reasonable RS characteristics. This work provides a promising material strategy for lead-free all-inorganic HP-based nonvolatile memory devices for practical applications.

Coexisting hidden and self-excited attractors in a locally active memristor-based circuit

This paper presents a chaotic circuit based on a nonvolatile locally active memristor model, with non-volatility and local activity verified by the power-off plot and the DC V-I plot, respectively. It is shown that the memristor-based circuit has no equilibrium with appropriate parameter values and can exhibit three hidden coexisting heterogeneous attractors including point attractors, periodic attractors, and chaotic attractors. As is well known, for a hidden attractor, its attraction basin does not intersect with any small neighborhood of any unstable equilibrium. However, it is found that some attractors of this circuit can be excited from an unstable equilibrium in the locally active region of the memristor, meaning that its basin of attraction intersects with neighborhoods of an unstable equilibrium of the locally active memristor. Furthermore, with another set of parameter values, the circuit possesses three equilibria and can generate self-excited chaotic attractors. Theoretical and simulated analyses both demonstrate that the local activity and an unstable equilibrium of the memristor are two reasons for generating hidden attractors by the circuit. This chaotic circuit is implemented in a digital signal processing circuit experiment to verify the theoretical analysis and numerical simulations.

Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations

A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS₂ FET can be tuned by applying an up-gate voltage pulse, which can vary the channel conductance to exhibit memory states. Through controlling the amounts of triggered molecules through either different gate voltage pulses or gate duration time, multilevel states were obtained in the molecular memory. These new molecular memory transistors exhibited an erase/program ratio of more than three orders of current magnitude and high sensitivity, of a few picoamperes, at the current level. Reproducible operation and four-level states with stable retention and endurance were achieved. We believe this prototype device has potential for use in future memory devices.

A gate-tunable symmetric bipolar junction transistor fabricated via femtosecond laser processing

Two-dimensional (2D) bipolar junction transistors (BJTs) with van der Waals heterostructures play an important role in the development of future nanoelectronics. Herein, a convenient method is introduced for fabricating a symmetric bipolar junction transistor (SBJT), constructed from black phosphorus and MoS₂, with femtosecond laser processing. This SBJT exhibits good bidirectional current amplification owing to its symmetric structure. We placed a top gate on one side of the SBJT to change the difference in the major carrier concentration between the emitter and collector in order to further investigate the effects of electrostatic doping on the device performance. The SBJT can also act as a gate-tunable phototransistor with good photodetectivity and photocurrent gain of β = ∼21. Scanning photocurrent images were used to determine the mechanism governing photocurrent amplification in the phototransistor. These results promote the development of the applications of multifunctional nanoelectronics based on 2D materials.

Self-Compliance and High Performance Pt/HfOx/Ti RRAM Achieved through Annealing

A self-compliance resistive random access memory (RRAM) achieved through thermal annealing of a Pt/HfO_x/Ti structure. The electrical characteristic measurements show that the forming voltage of the device annealing at 500 °C decreased, and the switching ratio and uniformity improved. Tests on the device’s cycling endurance and data retention characteristics found that the device had over 1000 erase/write endurance and over 10⁵ s of lifetime (85 °C). The switching mechanisms of the devices before and after annealing were also discussed.

Ultrafast machine vision with 2D material neural network image sensors

Machine vision technology has taken huge leaps in recent years, and is now becoming an integral part of various intelligent systems, including autonomous vehicles and robotics. Usually, visual information is captured by a frame-based camera, converted into a digital format and processed afterwards using a machine-learning algorithm such as an artificial neural network (ANN)¹. The large amount of (mostly redundant) data passed through the entire signal chain, however, results in low frame rates and high power consumption. Various visual data preprocessing techniques have thus been developed^2-7 to increase the efficiency of the subsequent signal processing in an ANN. Here we demonstrate that an image sensor can itself constitute an ANN that can simultaneously sense and process optical images without latency. Our device is based on a reconfigurable two-dimensional (2D) semiconductor^8,9 photodiode^10-12 array, and the synaptic weights of the network are stored in a continuously tunable photoresponsivity matrix. We demonstrate both supervised and unsupervised learning and train the sensor to classify and encode images that are optically projected onto the chip with a throughput of 20 million bins per second.

Global Stabilization of Fractional-Order Memristor-Based Neural Networks With Time Delay

This paper addresses the global stabilization of fractional-order memristor-based neural networks (FMNNs) with time delay. The voltage threshold type memristor model is considered, and the FMNNs are represented by fractional-order differential equations with discontinuous right-hand sides. Then, the problem is addressed based on fractional-order differential inclusions and set-valued maps, together with the aid of Lyapunov functions and the comparison principle. Two types of control laws (delayed state feedback control and coupling state feedback control) are designed. Accordingly, two types of stabilization criteria [algebraic form and linear matrix inequality (LMI) form] are established. There are two groups of adjustable parameters included in the delayed state feedback control, which can be selected flexibly to achieve the desired global asymptotic stabilization or global Mittag-Leffler stabilization. Since the existing LMI-based stability analysis techniques for fractional-order systems are not applicable to delayed fractional-order nonlinear systems, a fractional-order differential inequality is established to overcome this difficulty. Based on the coupling state feedback control, some LMI stabilization criteria are developed for the first time with the help of the newly established fractional-order differential inequality. The obtained LMI results provide new insights into the research of delayed fractional-order nonlinear systems. Finally, three numerical examples are presented to illustrate the effectiveness of the proposed theoretical results.

A Low-Current and Analog Memristor with Ru as Mobile Species

The switching parameters and device performance of memristors are predominately determined by their mobile species and matrix materials. Devices with oxygen or oxygen vacancies as the mobile species usually exhibit a great retention but also need a relatively high switching current (e.g., >30 µA), while devices with Ag or Cu as cation mobile species do not require a high switching current but usually show a poor retention. Here, Ru is studied as a new type of mobile species for memristors to achieve low switching current, fast speed, good reliability, scalability, and analog switching property simultaneously. An electrochemical metallization-like memristor with a stack of Pt/Ta₂ O₅ /Ru is developed. Migration of Ru ions is revealed by energy-dispersive X-ray spectroscopy mapping and in situ transmission electron microscopy within a sub-10 nm active device area before and after switching. The results open up a new avenue to engineer memristors for desired properties.

On-Chip TaO x -Based Non-volatile Resistive Memory for in vitro Neurointerfaces

The development of highly integrated electrophysiological devices working in direct contact with living neuron tissue opens new exciting prospects in the fields of neurophysiology and medicine, but imposes tight requirements on the power dissipated by electronics. On-chip preprocessing of neuronal signals can substantially decrease the power dissipated by external data interfaces, and the addition of embedded non-volatile memory would significantly improve the performance of a co-processor in real-time processing of the incoming information stream from the neuron tissue. Here, we evaluate the parameters of TaO _x -based resistive switching (RS) memory devices produced by magnetron sputtering technique and integrated with the 180-nm CMOS field-effect transistors as possible candidates for on-chip memory in the hybrid neurointerface under development. The electrical parameters of the optimized one-transistor-one-resistor (1T-1R) devices, such as the switching voltage (approx. ±1 V), uniformity of the R _off/R _on ratio (∼10), read/write speed (<40 ns), and the number of the writing cycles (up to 10¹⁰), are satisfactory. The energy values for writing and reading out a bit ∼30 and ∼0.1 pJ, respectively, are also suitable for the desired in vitro neurointerfaces, but are still far too high once the prospective in vivo applications are considered. Challenges arising in the course of the prospective fabrication of the proposed TaO _x -based RS devices in the back-end-of-line process are identified.

Analog Switching and Artificial Synaptic Behavior of Ag/SiOx:Ag/TiOx/p++-Si Memristor Device

In this study, by inserting a buffer layer of TiO_x between the SiO_x:Ag layer and the bottom electrode, we have developed a memristor device with a simple structure of Ag/SiO_x:Ag/TiO_x/p⁺⁺-Si by a physical vapor deposition process, in which the filament growth and rupture can be efficiently controlled during analog switching. The synaptic characteristics of the memristor device with a wide range of resistance change for weight modulation by implementing positive or negative pulse trains have been investigated extensively. Several learning and memory functions have been achieved simultaneously, including potentiation/depression, paired-pulse-facilitation (PPF), short-term plasticity (STP), and STP-to-LTP (long-term plasticity) transition controlled by repeating pulses more than a rehearsal operation, and spike-time-dependent-plasticity (STDP) as well. Based on the analysis of logarithmic I-V characteristics, it has been found that the controlled evolution/dissolution of conductive Ag-filaments across the dielectric layers can improve the performance of the testing memristor device.

Multi-level anomalous Hall resistance in a single Hall cross for the applications of neuromorphic device

We demonstrate the process of obtaining memristive multi-states Hall resistance (R_H) change in a single Hall cross (SHC) structure. Otherwise, the working mechanism successfully mimics the behavior of biological neural systems. The motion of domain wall (DW) in the SHC was used to control the ascend (or descend) of the R_H amplitude. The primary synaptic functions such as long-term potentiation (LTP), long-term depression (LTD), and spike-time-dependent plasticity (STDP) could then be emulated by regulating R_H. Applied programmable magnetic field pulses are in varying conditions such as intensity and duration to adjust R_H. These results show that analog readings of DW movement can be closely resembled with the change of synaptic weight and have great potentials for bioinspired neuromorphic computing.

Self-adaptive STDP-based learning of a spiking neuron with nanocomposite memristive weights

Neuromorphic systems consisting of artificial neurons and memristive synapses could provide a much better performance and a significantly more energy-efficient approach to the implementation of different types of neural network algorithms than traditional hardware with the Von-Neumann architecture. However, the memristive weight adjustment in the formal neuromorphic networks by the standard back-propagation techniques suffers from poor device-to-device reproducibility. One of the most promising approaches to overcome this problem is to use local learning rules for spiking neuromorphic architectures which potentially could be adaptive to the variability issue mentioned above. Different kinds of local rules for learning spiking systems are mostly realized on a bio-inspired spike-time-dependent plasticity (STDP) mechanism, which is an improved type of classical Hebbian learning. Whereas the STDP-like mechanism has already been shown to emerge naturally in memristive devices, the demonstration of its self-adaptive learning property, potentially overcoming the variability problem, is more challenging and has yet to be reported. Here we experimentally demonstrate an STDP-based learning protocol that ensures self-adaptation of the memristor resistive states, after only a very few spikes, and makes the plasticity sensitive only to the input signal configuration, but neither to the initial state of the devices nor their device-to-device variability. Then, it is shown that the self-adaptive learning of a spiking neuron with memristive weights on rate-coded patterns could also be realized with hardware-based STDP rules. The experiments have been carried out with nanocomposite-based (Co₄₀Fe₄₀B₂₀) _х (LiNbO_3-y )_100-х memristive structures, but their results are believed to be applicable to a wide range of memristive devices. All the experimental data were supported and extended by numerical simulations. There is a hope that the obtained results pave the way for building up reliable spiking neuromorphic systems composed of partially unreliable analog memristive elements, with a more complex architecture and the capability of unsupervised learning.

Design and characterization of superconducting nanowire-based processors for acceleration of deep neural network training

Training of deep neural networks (DNNs) is a computationally intensive task and requires massive volumes of data transfer. Performing these operations with the conventional von Neumann architectures creates unmanageable time and power costs. Recent studies have shown that mixed-signal designs involving resistive crossbar architectures are capable of achieving acceleration factors as high as 30 000 × over the state of the art digital processors. These approaches involve utilization of non-volatile memory elements as local processors. However, no technology has been developed to-date that can satisfy the strict device requirements for the unit cell. This paper presents the superconducting nanowire-based processing element as a crosspoint device. The unit cell has many programmable non-volatile states that can be used to perform analog multiplication. Importantly, these states are intrinsically discrete due to quantization of flux, which provides symmetric switching characteristics. Operation of these devices in a crossbar is described and verified with electro-thermal circuit simulations. Finally, validation of the concept in an actual DNN training task is shown using an emulator.

Neuromemristive Circuits for Edge Computing: A Review

The volume, veracity, variability, and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks, and open problems in the field of neuromemristive circuits for edge computing.

A neuromorphic systems approach to in-memory computing with non-ideal memristive devices: from mitigation to exploitation

Memristive devices represent a promising technology for building neuromorphic electronic systems. In addition to their compactness and non-volatility, they are characterized by their computationally relevant physical properties, such as their state-dependence, non-linear conductance changes, and intrinsic variability in both their switching threshold and conductance values, that make them ideal devices for emulating the bio-physics of real synapses. In this paper we present a spiking neural network architecture that supports the use of memristive devices as synaptic elements and propose mixed-signal analog-digital interfacing circuits that mitigate the effect of variability in their conductance values and exploit their variability in the switching threshold for implementing stochastic learning. The effect of device variability is mitigated using pairs of memristive devices configured in a complementary push-pull mechanism and interfaced to a current-mode normalizer circuit. The stochastic learning mechanism is obtained by mapping the desired change in synaptic weight into a corresponding switching probability that is derived from the intrinsic stochastic behavior of memristive devices. We demonstrate the features of the CMOS circuits and apply the architecture proposed to a standard neural network hand-written digit classification benchmark based on the MNIST data-set. We evaluate the performance of the approach proposed in this benchmark using behavioral-level spiking neural network simulation, showing both the effect of the reduction in conductance variability produced by the current-mode normalizer circuit and the increase in performance as a function of the number of memristive devices used in each synapse.

Time and rate dependent synaptic learning in neuro-mimicking resistive memories

Memristors have demonstrated immense potential as building blocks in future adaptive neuromorphic architectures. Recently, there has been focus on emulating specific synaptic functions of the mammalian nervous system by either tailoring the functional oxides or engineering the external programming hardware. However, high device-to-device variability in memristors induced by the electroforming process and complicated programming hardware are among the key challenges that hinder achieving biomimetic neuromorphic networks. Here, a simple hybrid complementary metal oxide semiconductor (CMOS)-memristor approach is reported to implement different synaptic learning rules by utilizing a CMOS-compatible memristor based on oxygen-deficient SrTiO3-x (STOx). The potential of such hybrid CMOS-memristor approach is demonstrated by successfully imitating time-dependent (pair and triplet spike-time-dependent-plasticity) and rate-dependent (Bienenstosk-Cooper-Munro) synaptic learning rules. Experimental results are benchmarked against in-vitro measurements from hippocampal and visual cortices with good agreement. The scalability of synaptic devices and their programming through a CMOS drive circuitry elaborates the potential of such an approach in realizing adaptive neuromorphic computation and networks.

Emergent dynamics of neuromorphic nanowire networks

Neuromorphic networks are formed by random self-assembly of silver nanowires. Silver nanowires are coated with a polymer layer after synthesis in which junctions between two nanowires act as resistive switches, often compared with neurosynapses. We analyze the role of single junction switching in the dynamical properties of the neuromorphic network. Network transitions to a high-conductance state under the application of a voltage bias higher than a threshold value. The stability and permanence of this state is studied by shifting the voltage bias in order to activate or deactivate the network. A model of the electrical network with atomic switches reproduces the relation between individual nanowire junctions switching events with current pathway formation or destruction. This relation is further manifested in changes in 1/f power-law scaling of the spectral distribution of current. The current fluctuations involved in this scaling shift are considered to arise from an essential equilibrium between formation, stochastic-mediated breakdown of individual nanowire-nanowire junctions and the onset of different current pathways that optimize power dissipation. This emergent dynamics shown by polymer-coated Ag nanowire networks places this system in the class of optimal transport networks, from which new fundamental parallels with neural dynamics and natural computing problem-solving can be drawn.

A Silicon-Compatible Synaptic Transistor Capable of Multiple Synaptic Weights toward Energy-Efficient Neuromorphic Systems

In order to resolve the issue of tremendous energy consumption in conventional artificial intelligence, hardware-based neuromorphic system is being actively studied. Although various synaptic devices for the system have been proposed, they have shown limits in terms of endurance, reliability, energy efficiency, and Si processing compatibility. In this work, we design a synaptic transistor with short-term and long-term plasticity, high density, high reliability and energy efficiency, and Si processing compatibility. The synaptic characteristics of the device are closely examined and validated through technology computer-aided design (TCAD) device simulation. Consequently, full synaptic functions with high energy efficiency have been realized.

Nitrogen-Induced Enhancement of Synaptic Weight Reliability in Titanium Oxide-Based Resistive Artificial Synapse and Demonstration of the Reliability Effect on the Neuromorphic System

With the significant technological developments in recent times, the neuromorphic system has been receiving considerable attention owing to its parallel arithmetic, low power consumption, and high scalability. However, the low reliability of artificial synapse devices disturbs calculations and causes inaccurate results in neuromorphic systems. In this paper, we propose a stable resistive artificial synapse (RAS) device with nitrogen-doped titanium oxide (TiO_x:N)-based resistive switching (RS) memory. The TiO_x:N-based RAS, compared to the TiO_x-based RAS, demonstrates more stable RS characteristics in current-voltage (I-V) and pulse measurements. In terms of resistance variability, the TiO_x:N-based RAS demonstrates five times lower resistance variability at 1.38%, compared to 6.68% with the TiO_x-based RAS. In addition, we verified the relation between the neuromorphic system and the resistance reliability of the synapse device for the first time. The pattern recognition simulation is performed using an artificial neural network (ANN) consisting of artificial synapse devices using the Modified National Institute of Standards and Technology dataset. In the simulation, the ANN with the TiO_x:N-based RAS exhibited significant pattern recognition accuracy of 64.41%, while the ANN with TiO_x-based RAS demonstrated only low recognition accuracy of 22.07%. According to the results of subsequent simulations, the pattern recognition accuracy exponentially decreases when the resistance variability exceeds 5%. Therefore, for implementing a stable neuromorphic system, the synapse device in the neuromorphic system has to maintain low resistance variability. The proposed nitrogen-doped synapse device is suitable for neuromorphic systems because reliable resistance variability can be obtained with only simple process steps.

Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal-Oxide-Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

Memristor Neural Network Training with Clock Synchronous Neuromorphic System

Memristor devices are considered to have the potential to implement unsupervised learning, especially spike timing-dependent plasticity (STDP), in the field of neuromorphic hardware research. In this study, a neuromorphic hardware system for multilayer unsupervised learning was designed, and unsupervised learning was performed with a memristor neural network. We showed that the nonlinear characteristic memristor neural network can be trained by unsupervised learning only with the correlation between inputs and outputs. Moreover, a method to train nonlinear memristor devices in a supervised manner, named guide training, was devised. Memristor devices have a nonlinear characteristic, which makes implementing machine learning algorithms, such as backpropagation, difficult. The guide-training algorithm devised in this paper updates the synaptic weights by only using the correlations between inputs and outputs, and therefore, neither complex mathematical formulas nor computations are required during the training. Thus, it is considered appropriate to train a nonlinear memristor neural network. All training and inference simulations were performed using the designed neuromorphic hardware system. With the system and memristor neural network, the image classification was successfully done using both the Hebbian unsupervised training and guide supervised training methods.

Nanopatterns with a Square Symmetry from an Orthogonal Lamellar Assembly of Block Copolymers

A nanosquare array is an indispensable element for the integrated circuit design of electronic devices. Block copolymer (BCP) lithography, a promising bottom-up approach for sub-10 nm patterning, has revealed a generic difficulty in the production of square symmetry because of the thermodynamically favored hexagonal packing of self-assembled sphere or cylinder arrays in thin-film geometry. Here, we demonstrate a simple route to square arrays via the orthogonal self-assembly of two lamellar layers on topographically patterned substrates. While bottom lamellar layers within a topographic trench are aligned parallel to the sidewalls, top layers above the trench are perpendicularly oriented to relieve the interfacial energy between grain boundaries. The size and period of the square symmetry are readily controllable with the molecular weight of BCPs. Moreover, such an orthogonal self-assembly can be applied to the formation of complex nanopatterns for advanced applications, including metal nanodot square arrays.

Electron Beam Effects on Oxide Thin Films-Structure and Electrical Property Correlations

In situ transmission electron microscope (TEM) characterization techniques provide valuable information on structure-property correlations to understand the behavior of materials at the nanoscale. However, understanding nanoscale structures and their interaction with the electron beam is pivotal for the reliable interpretation of in situ/ex situ TEM studies. Here, we report that oxides commonly used in nanoelectronic applications, such as transistor gate oxides or memristive devices, are prone to electron beam induced damage that causes small structural changes even under very low dose conditions, eventually changing their electrical properties as examined via in situ measurements. In this work, silicon, titanium, and niobium oxide thin films are used for in situ TEM electrical characterization studies. The electron beam induced reduction of the oxides turns these insulators into conductors. The conductivity change is reversible by exposure to air, supporting the idea of electron beam reduction of oxides as primary damage mechanism. Through these measurements we propose a limit for the critical dose to be considered for in situ scanning electron microscopy and TEM characterization studies.

Thermally Stable Amorphous Oxide-based Schottky Diodes through Oxygen Vacancy Control at Metal/Oxide Interfaces

Amorphous oxide semiconductor (AOS)-based Schottky diodes have been utilized for selectors in crossbar array memories to improve cell-to-cell uniformity with a low-temperature process. However, thermal instability at interfaces between the AOSs and metal electrodes can be a critical issue for the implementation of reliable Schottky diodes. Under post-fabrication annealing, an excessive redox reaction at the ohmic interface can affect the bulk region of the AOSs, inducing an electrical breakdown of the device. Additionally, structural relaxation (SR) of the AOSs can increase the doping concentration at the Schottky interface, which results in a degradation of the rectifying performance. Here, we improved the thermal stability at AOS/metal interfaces by regulating the oxygen vacancy (V_O) concentration at both sides of the contact. For a stable quasi-ohmic contact, a Cu-Mn alloy was introduced instead of a single component reactive metal. As Mn only takes up O in amorphous In-Ga-Zn-O (a-IGZO), excessive V_O generation in bulk region of a-IGZO can be prevented. At the Schottky interfaces, the barrier characteristics were not degraded by thermal annealing as the Ga concentration in a-IGZO increased. Ga not only reduces the inherent V_O concentration but also retards SR, thereby suppressing tunneling conduction and enhancing the thermal stability of devices.

Optically Stimulated Artificial Synapse Based on Layered Black Phosphorus

The translation of biological synapses onto a hardware platform is an important step toward the realization of brain-inspired electronics. However, to mimic biological synapses, devices till-date continue to rely on the need for simultaneously altering the polarity of an applied electric field or the output of these devices is photonic instead of an electrical synapse. As the next big step toward practical realization of optogenetics inspired circuits that exhibit fidelity and flexibility of biological synapses, optically-stimulated synaptic devices without a need to apply polarity-altering electric field are needed. Utilizing a unique photoresponse in black phosphorus (BP), here reported is an all-optical pathway to emulate excitatory and inhibitory action potentials by exploiting oxidation-related defects. These optical synapses are capable of imitating key neural functions such as psychological learning and forgetting, spatiotemporally correlated dynamic logic and Hebbian spike-time dependent plasticity. These functionalities are also demonstrated on a flexible platform suitable for wearable electronics. Such low-power consuming devices are highly attractive for deployment in neuromorphic architectures. The manifestation of cognition and spatiotemporal processing solely through optical stimuli provides an incredibly simple and powerful platform to emulate sophisticated neural functionalities such as associative sensory data processing and decision making.

Perovskite-related (CH3NH3)3Sb2Br9 for forming-free memristor and low-energy-consuming neuromorphic computing

Organic-inorganic halide perovskite materials exhibit excellent memristive properties, such as a high on/off ratio and low switching voltage. However, most studies have focused on Pb-based perovskites. Here, we report on the resistive switching and neuromorphic computing properties of Pb-free perovskite-related MA3Sb2Br9 (MA = CH3NH3). The Ag/PMMA/MA3Sb2Br9/ITO devices show forming-free characteristics due to a self-formed conducting filament induced by metallic Sb present in the as-prepared MA3Sb2Br9 layer. An MA3Sb2Br9-based memristor exhibits a reliable on/off ratio (∼102), an endurance of 300 cycles, a retention time of ∼104 s and multilevel storage characteristics. Furthermore, synaptic characteristics, such as short-term potentiation, short-term depression and long-term potentiation, are revealed along with a low energy-consumption of 117.9 fJ μm-2, which indicates that MA3Sb2Br9 is a promising material for neuromorphic computing.

Complementary Resistive Switching Using Metal-Ferroelectric-Metal Tunnel Junctions

Complementary resistive switching (CRS) devices are receiving attention because they can potentially solve the current-sneak and current-leakage problems of memory arrays based on resistive switching (RS) elements. It is shown here that a simple anti-serial connection of two ferroelectric tunnel junctions, based on BaTiO₃ , with symmetric top metallic electrodes and a common, floating bottom nanometric film electrode, constitute a CRS memory element. It allows nonvolatile storage of binary states ("1" = "HRS+LRS" and "0" = "LRS+HRS"), where HRS (LRS) indicate the high (low) resistance state of each ferroelectric tunnel junction. Remarkably, these states have an identical and large resistance in the remanent state, characteristic of CRS. Here, protocols for writing information are reported and it is shown that non-destructive or destructive reading schemes can be chosen by selecting the appropriate reading voltage amplitude. Moreover, this dual-tunnel device has a significantly lower power consumption than a single ferroelectric tunnel junction to perform writing/reading functions, as is experimentally demonstrated. These findings illustrate that the recent impressive development of ferroelectric tunnel junctions can be further exploited to contribute to solving critical bottlenecks in data storage and logic functions implemented using RS elements.

Resistivity control by the electrochemical removal of dopant atoms from a nanodot

Doping impurity atoms into semiconductor materials changes the resistance of the material. Selecting the atomic species of a dopant and the precise control of the number of dopant atoms in a unit volume can control the resistance to a desired value. The number of dopant atoms is usually controlled when the materials are synthesized. It can also be controlled after synthesizing by injecting dopant atoms using an ion implantation technique. This physical method has now enabled atom by atom implantation at the desired position. Here, we propose an additional technique, based on the electrochemical potential of dopant atoms in a material. The technique enables the dynamic control of the number of dopant atoms through the application of bias to the material. We demonstrate the controlled removal of dopant atoms using Ag2+δS and Ag-doped Ta2O5 as model materials. The change in resistance accompanying the removal of dopant atoms is also observed.

Transient bioelectrical devices inspired by a silkworm moth breaking out of its cocoon

Transient devices have attracted extensive interest because they allow changes in physical form and device function under the control of external stimuli or related commands and have very broad application prospects for information security, biomedical care and the environment. Transient bioelectrical devices were fabricated inspired by a silkworm moth breaking out of its cocoon, which has shown many advantages, including the use of mild stimulation, biocompatible materials, a simple process, and a universal strategy. For the fabrication of the transient devices, heat-sensitive microspheres with a 9.3 mol L⁻¹ LiBr solution in wax shells were prepared by microfluidic technology, which were then assembled into silk fibroin (SF) electronic materials/devices, such as SF conductive film, an LED circuit on SF film, and a Ag/SF film/Pt/SF film memristor. The contribution from the LiBr/wax microspheres to the transient time of the SF films upon exposure to heat was quantitatively investigated. This approach was applied to transiently dissolve a flexible Ag-nanowire resistance circuit line on a SF substrate. Moreover, memristors constructed with a functional layer of SF were destroyed by melting the LiBr/wax microspheres. This technique paves the way for realizing transient bioelectrical devices inspired by biological behavior, which have been well optimized by nature via evolution.

Silk fibroin-based transient devices were developed using LiBr/wax microspheres that mimic a silk cocoon protecting silkworm pupa and a juvenile moth secreting an enzyme to dissolve silk sericin and break a silk cocoon.

Solution-Processable ZnO Thin Film Memristive Device for Resistive Random Access Memory Application

The memristive device is a fourth fundamental circuit element with inherent memory, nonlinearity, and passivity properties. Herein, we report on a cost-effective and rapidly produced ZnO thin film memristive device using the doctor blade method. The active layer of the developed device (ZnO) was composed of compact microrods. Furthermore, ZnO microrods were well spread horizontally and covered the entire surface of the fluorine-doped tin oxide substrate. X-ray diffraction (XRD) results confirmed that the synthesized ZnO was oriented along the c-axis and possessed a hexagonal crystal structure. The device showed bipolar resistive switching characteristics and required a very low resistive switching voltage (±0.8 V) for its operation. Two distinct and well-resolved resistance states with a remarkable 103 memory window were achieved at 0.2-V read voltage. The developed device switched successfully in consecutive 102 switching cycles and was stable over 102 seconds without any observable degradation in the resistive switching states. In addition to this, the charge–magnetic flux curve was observed to be a single-valued function at a higher magnitude of the flux and became double valued at a lower magnitude of the flux. The conduction mechanism of the ZnO thin film memristive device followed the space charge limited current, and resistive switching was due to the filamentary resistive switching effect.

Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain

Neuromorphic engineering (NE) encompasses a diverse range of approaches to information processing that are inspired by neurobiological systems, and this feature distinguishes neuromorphic systems from conventional computing systems. The brain has evolved over billions of years to solve difficult engineering problems by using efficient, parallel, low-power computation. The goal of NE is to design systems capable of brain-like computation. Numerous large-scale neuromorphic projects have emerged recently. This interdisciplinary field was listed among the top 10 technology breakthroughs of 2014 by the MIT Technology Review and among the top 10 emerging technologies of 2015 by the World Economic Forum. NE has two-way goals: one, a scientific goal to understand the computational properties of biological neural systems by using models implemented in integrated circuits (ICs); second, an engineering goal to exploit the known properties of biological systems to design and implement efficient devices for engineering applications. Building hardware neural emulators can be extremely useful for simulating large-scale neural models to explain how intelligent behavior arises in the brain. The principal advantages of neuromorphic emulators are that they are highly energy efficient, parallel and distributed, and require a small silicon area. Thus, compared to conventional CPUs, these neuromorphic emulators are beneficial in many engineering applications such as for the porting of deep learning algorithms for various recognitions tasks. In this review article, we describe some of the most significant neuromorphic spiking emulators, compare the different architectures and approaches used by them, illustrate their advantages and drawbacks, and highlight the capabilities that each can deliver to neural modelers. This article focuses on the discussion of large-scale emulators and is a continuation of a previous review of various neural and synapse circuits (Indiveri et al., 2011). We also explore applications where these emulators have been used and discuss some of their promising future applications.

Rectifying Resistive Memory Devices as Dynamic Complementary Artificial Synapses

Brain inspired computing is a pioneering computational method gaining momentum in recent years. Within this scheme, artificial neural networks are implemented using two main approaches: software algorithms and designated hardware architectures. However, while software implementations show remarkable results (at high-energy costs), hardware based ones, specifically resistive random access memory (RRAM) arrays that consume little power and hold a potential for enormous densities, are somewhat lagging. One of the reasons may be related to the limited excitatory operation mode of RRAMs in these arrays as adjustable passive elements. An interesting type of RRAM was demonstrated recently for having alternating (dynamic switching) current rectification properties that may be used for complementary operation much like CMOS transistors. Such artificial synaptic devices may be switched dynamically between excitatory and inhibitory modes to allow doubling of the array density and significantly reducing the peripheral circuit complexity.

An Analytical Comparison of Locally-Connected Reconfigurable Neural Network Architectures Using a C. elegans Locomotive Model

The scale of modern neural networks is growing rapidly, with direct hardware implementations providing significant speed and energy improvements over their software counterparts. However, these hardware implementations frequently assume global connectivity between neurons and thus suffer from communication bottlenecks. Such issues are not found in biological neural networks. It should therefore be possible to develop new architectures to reduce the dependence on global communications by considering the connectivity of biological networks. This paper introduces two reconfigurable locally-connected architectures for implementing biologically inspired neural networks in real time. Both proposed architectures are validated using the segmented locomotive model of the C. elegans, performing a demonstration of forwards, backwards serpentine motion and coiling behaviours. Local connectivity is discovered to offer up to a 17.5× speed improvement over hybrid systems that use combinations of local and global infrastructure. Furthermore, the concept of locality of connections is considered in more detail, highlighting the importance of dimensionality when designing neuromorphic architectures. Convolutional Neural Networks are shown to map poorly to locally connected architectures despite their apparent local structure, and both the locality and dimensionality of new neural processing systems is demonstrated as a critical component for matching the function and efficiency seen in biological networks.

Aligned Carbon Nanotube Synaptic Transistors for Large-Scale Neuromorphic Computing

This paper presents aligned carbon nanotube (CNT) synaptic transistors for large-scale neuromorphic computing systems. The synaptic behavior of these devices is achieved via charge-trapping effects, commonly observed in carbon-based nanoelectronics. In this work, charge trapping in the high- k dielectric layer of top-gated CNT field-effect transistors (FETs) enables the gradual analog programmability of the CNT channel conductance with a large dynamic range ( i. e., large on/off ratio). Aligned CNT synaptic devices present significant improvements over conventional memristor technologies ( e. g., RRAM), which suffer from abrupt transitions in the conductance modulation and/or a small dynamic range. Here, we demonstrate exceptional uniformity of aligned CNT FET synaptic behavior, as well as significant robustness and nonvolatility via pulsed experiments, establishing their suitability for neural network implementations. Additionally, this technology is based on a wafer-level technique for constructing highly aligned arrays of CNTs with high semiconducting purity and is fully CMOS compatible, ensuring the practicality of large-scale CNT+CMOS neuromorphic systems. We also demonstrate fine-tunability of the aligned CNT synaptic behavior and discuss its application to adaptive online learning schemes and to homeostatic regulation of artificial neuron firing rates. We simulate the implementation of unsupervised learning for pattern recognition using a spike-timing-dependent-plasticity scheme, indicate system-level performance (as indicated by the recognition accuracy), and demonstrate improvements in the learning rate resulting from tuning the synaptic characteristics of aligned CNT devices.

Nanoscale Conductive Filament with Alternating Rectification as an Artificial Synapse Building Block

A popular approach for resistive memory (RRAM)-based hardware implementation of neural networks utilizes one (or two) device that functions as an analog synapse in a crossbar structure of perpendicular pre- and postsynaptic neurons. An ideal fully automated, large-scale artificial neural network, which matches a biologic counterpart (in terms of density and energy consumption), thus requires nanosized, extremely low power devices with a wide dynamic range and multilevel functionality. Unfortunately the trade-off between these traits proves to be a serious obstacle in the realization of brain-inspired computing platforms yet to be overcome. This study demonstrates an alternative manner for the implementation of artificial synapses in which the local stoichiometry of metal oxide materials is delicately manipulated to form a single nanoscale conductive filament that may be used as a synaptic gap building block in an equivalent manner to the functionality of a single connexon (a signaling pore between synapses) with dynamic rectification direction. The structure, of a few nanometers in size, is based on the formation of defect states and shows current rectification properties that can be consecutively flipped to a forward or reverse direction to create either an excitatory or inhibitory (positive or negative) weight parameter. Alternatively, a plurality of these artificial connexons may be used to create a synthetic rectifying synaptic gap junction. In addition, the junction plasticity may be altered in a differential digital scheme (opposed to conventional analog RRAM conductivity manipulation) by changing the ratio of forward to reverse rectifying connexons.