High-Field Transport and Velocity Saturation in Synthetic Monolayer MoS2

Aligned carbon nanotube-based electronics on glass wafer

Carbon nanotubes (CNTs), due to excellent electronic properties, are emerging as a promising semiconductor for diverse electronic applications with superiority over silicon. However, until now, the supposed superiority of CNTs by "head-to-head" comparison within a well-defined voltage range remains unrealized. Here, we report aligned CNT (ACNT)-based electronics on a glass wafer and successfully develop a 250-nm gate length ACNT-based field-effect transistor (FET) with an almost identical transfer curve to a "90-nm" node silicon device, indicating a three- to four-generation superiority. Moreover, a record gate delay of 9.86 ps is achieved by our ring oscillator, which exceeds silicon even at a lower supply voltage. Furthermore, the fabrication of basic logic gates indicates the potential for further digital integrated circuits. All of these results highlight ACNT-based FETs on the glass wafer as an effective solution/platform for further development of CNT-based electronics.

High-Field Electron Transport and High Saturation Velocity in Multilayer Indium Selenide Transistors

Creating a high-frequency electron system demands a high saturation velocity (υsat). Herein, we report the high-field transport properties of multilayer van der Waals (vdW) indium selenide (InSe). The InSe is on a hexagonal boron nitride substrate and encapsulated by a thin, noncontinuous In layer, resulting in an impressive electron mobility reaching 2600 cm2/(V s) at room temperature. The high-mobility InSe achieves υsat exceeding 2 × 107 cm/s, which is superior to those of other gapped vdW semiconductors, and exhibits a 50-60% improvement in υsat when cooled to 80 K. The temperature dependence of υsat suggests an optical phonon energy (ℏωop) for InSe in the range of 23-27 meV, previously reported values for InSe. It is also notable that the measured υsat values exceed what is expected according to the optical phonon emission model due to weak electron-phonon scattering. The superior υsat of our InSe, despite its relatively small ℏωop, reveals its potential for high-frequency electronics, including applications to control cryogenic quantum computers in close proximity.

van der Waals Contact for Two-Dimensional Transition Metal Dichalcogenides

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as highly promising candidates for next-generation electronics owing to their atomically thin structures and surfaces devoid of dangling bonds. However, establishing high-quality metal contacts with TMDs presents a critical challenge, primarily attributed to their ultrathin bodies and delicate lattices. These distinctive characteristics render them susceptible to physical damage and chemical reactions when conventional metallization approaches involving "high-energy" processes are implemented. To tackle this challenge, the concept of van der Waals (vdW) contacts has recently been proposed as a "low-energy" alternative. Within the vdW geometry, metal contacts can be physically laminated or gently deposited onto the 2D channel of TMDs, ensuring the formation of atomically clean and electronically sharp contact interfaces while preserving the inherent properties of the 2D TMDs. Consequently, a considerable number of vdW contact devices have been extensively investigated, revealing unprecedented transport physics or exceptional device performance that was previously unachievable. This review presents recent advancements in vdW contacts for TMD transistors, discussing the merits, limitations, and prospects associated with each device geometry. By doing so, our purpose is to offer a comprehensive understanding of the current research landscape and provide insights into future directions within this rapidly evolving field.

Drain-Induced Multifunctional Ambipolar Electronics Based on Junctionless MoS2

Applying a drain bias to a strongly gate-coupled semiconductor influences the carrier density of the channel. However, practical applications of this drain-bias-induced effect in the advancement of switching electronics have remained elusive due to the limited capabilities of its current modulation known to date. Here, we show strategies to largely control the current by utilizing drain-bias-induced carrier type switching in an ambipolar molybdenum disulfide (MoS2) field-effect transistor with Pt bottom contacts. Our CMOS-compatible device architecture, incorporating a partially gate-coupled p-n junction, achieves multifunctionality. The ambipolar MoS2 device operates as an ambipolar transistor (on/off ratios exceeding 107 for both NMOS and PMOS), a rectifier (rectification ratio of ∼3 × 106), a reversible negative breakdown diode with an adjustable breakdown voltage (on/off ratio exceeding 109 with a maximum current as high as 10-4 A), and a photodetector. Finally, we demonstrate a complementary inverter (gain of ∼24 at Vdd = 1.5 V), which is highly facile to fabricate without the need for complex heterostructures and doping processes. Our study provides strategies to achieve high-performance ambipolar MoS2 devices and to effectively utilize drain bias for electrical switching.

Dielectrics for Two-Dimensional Transition-Metal Dichalcogenide Applications

Despite over a decade of intense research efforts, the full potential of two-dimensional transition-metal dichalcogenides continues to be limited by major challenges. The lack of compatible and scalable dielectric materials and integration techniques restrict device performances and their commercial applications. Conventional dielectric integration techniques for bulk semiconductors are difficult to adapt for atomically thin two-dimensional materials. This review provides a brief introduction into various common and emerging dielectric synthesis and integration techniques and discusses their applicability for 2D transition metal dichalcogenides. Dielectric integration for various applications is reviewed in subsequent sections including nanoelectronics, optoelectronics, flexible electronics, valleytronics, biosensing, quantum information processing, and quantum sensing. For each application, we introduce basic device working principles, discuss the specific dielectric requirements, review current progress, present key challenges, and offer insights into future prospects and opportunities.

Distinct Contact Scaling Effects in MoS2 Transistors Revealed with Asymmetrical Contact Measurements

2D semiconducting materials have immense potential for future electronics due to their atomically thin nature, which enables better scalability. While the channel scalability of 2D materials has been extensively studied, the current understanding of contact scaling in 2D devices is inconsistent and oversimplified. Here physically scaled contacts and asymmetrical contact measurements (ACMs) are combined to investigate the contact scaling behavior in 2D field-effect transistors. The ACMs directly compare electron injection at different contact lengths while using the exact same MoS₂  channel, eliminating channel-to-channel variations. The results show that scaled source contacts can limit the drain current, whereas scaled drain contacts do not. Compared to devices with long contact lengths, devices with short contact lengths (scaled contacts) exhibit larger variations, 15% lower drain currents at high drain-source voltages, and a higher chance of early saturation and negative differential resistance. Quantum transport simulations reveal that the transfer length of Ni-MoS₂  contacts can be as short as 5 nm. Furthermore, it is clearly identified that the actual transfer length depends on the quality of the metal-2D interface. The ACMs demonstrated here will enable further understanding of contact scaling behavior at various interfaces.

Physics-based bias-dependent compact modeling of 1/f noise in single- to few-layer 2D-FETs

1/f noise is a critical figure of merit for the performance of transistors and circuits. For two-dimensional devices (2D-FETs), and especially for applications in the GHz range where short-channel FETs are required, the velocity saturation (VS) effect can result in the reduction of 1/f noise at high longitudinal electric fields. A new physics-based compact model has been for the first time introduced for single- to few-layer 2D-FETs in this study, precisely validating 1/f noise experiments for various types of devices. The proposed model mainly accounts for the measured 1/f noise bias dependence as the latter is defined by different physical mechanisms. Thus, analytical expressions are derived, valid in all regions of operation in contrast to conventional approaches available in the literature so far, accounting for carrier number fluctuation (ΔN), mobility fluctuation (Δμ) and contact resistance (ΔR) effects based on the underlying physics that rules these devices. The ΔN mechanism due to trapping/detrapping together with an intense Coulomb scattering effect dominates the 1/f noise from the medium to the strong accumulation region while Δμ has also been demonstrated to modestly contribute in the subthreshold region. ΔR can also be significant in a very high carrier density. The VS induced reduction of 1/f noise measurements at high electric fields was also remarkably captured by the model. The physical validity of the model can also assist in extracting credible conclusions when conducting comparisons between experimental data from devices with different materials or dielectrics.

Ballistic two-dimensional InSe transistors

The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. 1). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm-1 and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V-1. Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.

Nanospike electrodes and charge nanoribbons: A new design for nanoscale thin-film transistors

To scale down thin-film transistor (TFT) channel lengths for accessing higher levels of speed and performance, a redesign of the basic device structure is necessary. With nanospike-shaped electrodes, field-emission effects can be used to assist charge injection from the electrodes in sub-200-nm channel length amorphous oxide and organic TFTs. These designs result in the formation of charge nanoribbons at low gate biases that greatly improve subthreshold and turn-off characteristics. A design paradigm in which the gate electric field can be less than the source-drain field is proposed and demonstrated. By combining small channel lengths and thick gate dielectrics, this approach is also shown to be a promising solution for boosting TFT performance through charge focusing and charge nanoribbon formation in flexible/printed electronics applications.

Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS2

Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS₂ films at 560 °C in 50 min, within the 450-to-600 °C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ∼140 μA/μm at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS₂ grown below 600 °C using solid-source precursors. The effective mobility from transfer length method test structures is 29 ± 5 cm² V^-1 s^-1 at 6.1 × 10¹² cm^-2 electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.

Impact of device scaling on the electrical properties of MoS2 field-effect transistors

Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS₂ material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS₂ transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

Promises and prospects of two-dimensional transistors

Two-dimensional (2D) semiconductors have attracted tremendous interest as atomically thin channels that could facilitate continued transistor scaling. However, despite many proof-of-concept demonstrations, the full potential of 2D transistors has yet to be determined. To this end, the fundamental merits and technological limits of 2D transistors need a critical assessment and objective projection. Here we review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking 2D transistors. We suggest that the saturation or on-state current density, especially in the short-channel limit, could provide a more reliable measure for assessing the potential of diverse 2D semiconductors, and should be applied for cross-checking different studies, especially when milestone performance metrics are claimed. We also summarize the key technical challenges in optimizing the channels, contacts, dielectrics and substrates and outline potential pathways to push the performance limit of 2D transistors. We conclude with an overview of the critical technical targets, the key technological obstacles to the 'lab-to-fab' transition and the potential opportunities arising from the use of these atomically thin semiconductors.

Benchmarking monolayer MoS2 and WS2 field-effect transistors

Here we benchmark device-to-device variation in field-effect transistors (FETs) based on monolayer MoS₂ and WS₂ films grown using metal-organic chemical vapor deposition process. Our study involves 230 MoS₂ FETs and 160 WS₂ FETs with channel lengths ranging from 5 μm down to 100 nm. We use statistical measures to evaluate key FET performance indicators for benchmarking these two-dimensional (2D) transition metal dichalcogenide (TMD) monolayers against existing literature as well as ultra-thin body Si FETs. Our results show consistent performance of 2D FETs across 1 × 1 cm² chips owing to high quality and uniform growth of these TMDs followed by clean transfer onto device substrates. We are able to demonstrate record high carrier mobility of 33 cm² V^-1 s^-1 in WS₂ FETs, which is a 1.5X improvement compared to the best reported in the literature. Our experimental demonstrations confirm the technological viability of 2D FETs in future integrated circuits.

High Current Density in Monolayer MoS2 Doped by AlOx

Semiconductors require stable doping for applications in transistors, optoelectronics, and thermoelectrics. However, this has been challenging for two-dimensional (2D) materials, where existing approaches are either incompatible with conventional semiconductor processing or introduce time-dependent, hysteretic behavior. Here we show that low-temperature (<200 °C) substoichiometric AlO_x provides a stable n-doping layer for monolayer MoS₂, compatible with circuit integration. This approach achieves carrier densities >2 × 10¹³ cm^-2, sheet resistance as low as ∼7 kΩ/□, and good contact resistance ∼480 Ω·μm in transistors from monolayer MoS₂ grown by chemical vapor deposition. We also reach record current density of nearly 700 μA/μm (>110 MA/cm²) along this three-atom-thick semiconductor while preserving transistor on/off current ratio >10⁶. The maximum current is ultimately limited by self-heating (SH) and could exceed 1 mA/μm with better device heat sinking. With their 0.1 nA/μm off-current, such doped MoS₂ devices approach several low-power transistor metrics required by the international technology roadmap.

Turn of the decade: versatility of 2D hexagonal boron nitride

The era of two-dimensional (2D) materials, in its current form, truly began at the time that graphene was first isolated just over 15 years ago. Shortly thereafter, the use of 2D hexagonal boron nitride (h-BN) had expanded in popularity, with use of the thin isolator permeating a significant number of fields in condensed matter and beyond. Due to the impractical nature of cataloguing every use or research pursuit, this review will cover ground in the following three subtopics relevant to this versatile material: growth, electrical measurements, and applications in optics and photonics. Through understanding how the material has been utilized, one may anticipate some of the exciting directions made possible by the research conducted up through the turn of this decade.

Field-effect at electrical contacts to two-dimensional materials

The inferior electrical contact to two-dimensional (2D) materials is a critical challenge for their application in post-silicon very large-scale integrated circuits. Electrical contacts were generally related to their resistive effect, quantified as contact resistance. With a systematic investigation, this work demonstrates a capacitive metal-insulator-semiconductor (MIS) field-effect at the electrical contacts to 2D materials: The field-effect depletes or accumulates charge carriers, redistributes the voltage potential, and gives rise to abnormal current saturation and nonlinearity. On one hand, the current saturation hinders the devices' driving ability, which can be eliminated with carefully engineered contact configurations. On the other hand, by introducing the nonlinearity to monolithic analog artificial neural network circuits, the circuits' perception ability can be significantly enhanced, as evidenced using a coronavirus disease 2019 (COVID-19) critical illness prediction model. This work provides a comprehension of the field-effect at the electrical contacts to 2D materials, which is fundamental to the design, simulation, and fabrication of electronics based on 2D materials.

ELECTRONIC SUPPLEMENTARY MATERIAL

Supplementary material (results of the simulation and SEM) is available in the online version of this article at 10.1007/s12274-021-3670-y.

Giant enhancement of exciton diffusivity in two-dimensional semiconductors

Two-dimensional (2D) semiconductors bear great promise for application in optoelectronic devices, but the low diffusivity of excitons stands as a notable challenge for device development. Here, we demonstrate that the diffusivity of excitons in monolayer MoS₂ can be improved from 1.5 ± 0.5 to 22.5 ± 2.5 square centimeters per second with the presence of trapped charges. This is manifested by a spatial expansion of photoluminescence when the incident power reaches a threshold value to enable the onset of exciton Mott transition. The trapped charges are estimated to be in a scale of 10¹⁰ per square centimeter and do not affect the emission features and recombination dynamics of the excitons. The result indicates that trapped charges provide an attractive strategy to screen exciton scattering with phonons and impurities/defects. Pointing towards a new pathway to control exciton transport and many-body interactions in 2D semiconductors.

Uncovering the Effects of Metal Contacts on Monolayer MoS2

Metal contacts are a key limiter to the electronic performance of two-dimensional (2D) semiconductor devices. Here, we present a comprehensive study of contact interfaces between seven metals (Y, Sc, Ag, Al, Ti, Au, Ni, with work functions from 3.1 to 5.2 eV) and monolayer MoS₂ grown by chemical vapor deposition. We evaporate thin metal films onto MoS₂ and study the interfaces by Raman spectroscopy, X-ray photoelectron spectroscopy, X-ray diffraction, transmission electron microscopy, and electrical characterization. We uncover that (1) ultrathin oxidized Al dopes MoS₂ n-type (>2 × 10¹² cm^-2) without degrading its mobility, (2) Ag, Au, and Ni deposition causes varying levels of damage to MoS₂ (e.g. broadening Raman E' peak from <3 to >6 cm^-1), and (3) Ti, Sc, and Y react with MoS₂. Reactive metals must be avoided in contacts to monolayer MoS₂, but control studies reveal the reaction is mostly limited to the top layer of multilayer films. Finally, we find that (4) thin metals do not significantly strain MoS₂, as confirmed by X-ray diffraction. These are important findings for metal contacts to MoS₂ and broadly applicable to many other 2D semiconductors.

Crystallized Monolayer Semiconductor for Ohmic Contact Resistance, High Intrinsic Gain, and High Current Density

The contact resistance limits the downscaling and operating range of organic field-effect transistors (OFETs). Access resistance through multilayers of molecules and the nonideal metal/semiconductor interface are two major bottlenecks preventing the lowering of the contact resistance. In this work, monolayer (1L) organic crystals and nondestructive electrodes are utilized to overcome the abovementioned challenges. High intrinsic mobility of 12.5 cm² V^-1 s^-1 and Ohmic contact resistance of 40 Ω cm are achieved. Unlike the thermionic emission in common Schottky contacts, the carriers are predominantly injected by field emission. The 1L-OFETs can operate linearly from V_DS  = -1 V to V_DS as small as -0.1 mV. Thanks to the good pinch-off behavior brought by the monolayer semiconductor, the 1L-OFETs show high intrinsic gain at the saturation regime. At a high bias load, a maximum current density of 4.2 µA µm^-1 is achieved by the only molecular layer as the active channel, with a current saturation effect being observed. In addition to the low contact resistance and high-resolution lithography, it is suggested that the thermal management of high-mobility OFETs will be the next major challenge in achieving high-speed densely integrated flexible electronics.

Fast growth of large-grain and continuous MoS2 films through a self-capping vapor-liquid-solid method

Most chemical vapor deposition methods for transition metal dichalcogenides use an extremely small amount of precursor to render large single-crystal flakes, which usually causes low coverage of the materials on the substrate. In this study, a self-capping vapor-liquid-solid reaction is proposed to fabricate large-grain, continuous MoS₂ films. An intermediate liquid phase-Na₂Mo₂O₇ is formed through a eutectic reaction of MoO₃ and NaF, followed by being sulfurized into MoS₂. The as-formed MoS₂ seeds function as a capping layer that reduces the nucleation density and promotes lateral growth. By tuning the driving force of the reaction, large mono/bilayer (1.1 mm/200 μm) flakes or full-coverage films (with a record-high average grain size of 450 μm) can be grown on centimeter-scale substrates. The field-effect transistors fabricated from the full-coverage films show high mobility (33 and 49 cm² V⁻¹ s⁻¹ for the mono and bilayer regions) and on/off ratio (1 ~ 5 × 10⁸) across a 1.5 cm × 1.5 cm region.

Here, the authors develop a self-capping vapour-liquid-solid reaction to fabricate large-grain continuous MoS₂ films, whereby an intermediate liquid phase-Na₂Mo₂O₇ is formed through a eutectic reaction of MoO₃ and NaF, followed by sulphurisation into MoS₂.

Lithium-ion electrolytic substrates for sub-1V high-performance transition metal dichalcogenide transistors and amplifiers

Electrostatic gating of two-dimensional (2D) materials with ionic liquids (ILs), leading to the accumulation of high surface charge carrier densities, has been often exploited in 2D devices. However, the intrinsic liquid nature of ILs, their sensitivity to humidity, and the stress induced in frozen liquids inhibit ILs from constituting an ideal platform for electrostatic gating. Here we report a lithium-ion solid electrolyte substrate, demonstrating its application in high-performance back-gated n-type MoS₂ and p-type WSe₂ transistors with sub-threshold values approaching the ideal limit of 60 mV/dec and complementary inverter amplifier gain of 34, the highest among comparable amplifiers. Remarkably, these outstanding values were obtained under 1 V power supply. Microscopic studies of the transistor channel using microwave impedance microscopy reveal a homogeneous channel formation, indicative of a smooth interface between the TMD and underlying electrolytic substrate. These results establish lithium-ion substrates as a promising alternative to ILs for advanced thin-film devices.

Electrostatic gating of 2D transistors with ionic liquids presents intrinsic limitations. Here, the authors demonstrate n-type MoS₂ and p-type WSe₂ transistors on a lithium-ion solid electrolyte substrate, displaying sub-threshold values approaching the ideal limit of 60 mV/dec and complementary amplifier gain of 34 with 1 V supply.

Current Rerouting Improves Heat Removal in Few-Layer WSe2 Devices

Few-layer (FL) transition-metal dichalcogenides have drawn attention for nanoelectronics applications due to their improved mobility, owing to the partial screening of charged impurities at the oxide interface. However, under realistic operating conditions, dissipation leads to self-heating, which is detrimental to electronic and thermal properties. We fabricated a series of FL-WSe₂ devices and measured their I-V characteristics, while their temperatures were quantified by Raman thermometry and simulated from first principles. Our tightly integrated electrothermal study shows that Joule heating leads to a significant layer-dependent temperature rise, which affects mobility and alters the flow of current through the stack. This causes the temperatures in the top layers to increase dramatically, degrading their mobility and causing the current to reroute to the bottom of the FL stack where thermal conductance is higher. We discover that this current rerouting phenomenon improves heat removal because the current flows through layers closer to the substrate, limiting the severity of self-heating and its impact on carrier mobility. We also observe significant lateral heat removal via the contacts because of longer thermal healing length in the top layers and explore the optimum number of layers to maximize mobility in FL devices. Our study will impact future device designs and lead to further improvements in thermal management in van der Waals (vdW)-based devices.

Ultrashort Vertical-Channel van der Waals Semiconductor Transistors

Atomically thin 2D van der Waals semiconductors are promising candidates for next-generation nanoscale field-effect transistors (FETs). Although large-area 2D van der Waals materials have been successfully synthesized, such nanometer-length-scale devices have not been well demonstrated in 2D van der Waals semiconductors. Here, controllable nanometer-scale transistors with a channel length of ≈10 nm are fabricated via vertical channels by squeezing an ultrathin insulating spacer between the out-of-plane source and drain electrodes, and the feasibility of high-density and large-scale fabrication is demonstrated. A large on-current density of ≈70 µA µm-1 nm-1 at a source-drain voltage of 0.5 V and a high on/off ratio of ≈107-109 are obtained in ultrashort 2D vertical channel FETs with monolayer MoS2 synthesized through chemical vapor deposition. The work provides a promising route toward the complementary metal-oxide-semiconductor-compatible fabrication of wafer-scale 2D van der Waals transistors with high-density integration.

Light Confinement Effect Induced Highly Sensitive, Self-Driven Near-Infrared Photodetector and Image Sensor Based on Multilayer PdSe2 /Pyramid Si Heterojunction

In this study, a highly sensitive and self-driven near-infrared (NIR) light photodetector based on PdSe₂ /pyramid Si heterojunction arrays, which are fabricated through simple selenization of predeposited Pd nanofilm on black Si, is demonstrated. The as-fabricated hybrid device exhibits excellent photoresponse performance in terms of a large on/off ratio of 1.6 × 10⁵ , a responsivity of 456 mA W^-1 , and a high specific detectivity of up to 9.97 × 10¹³ Jones under 980 nm illumination at zero bias. Such a relatively high sensitivity can be ascribed to the light trapping effect of the pyramid microstructure, which is confirmed by numerical modeling based on finite-difference time domain. On the other hand, thanks to the broad optical absorption properties of PdSe₂ , the as-fabricated device also exhibits obvious sensitivity to other NIR illuminations with wavelengths of 1300, 1550, and 1650 nm, which is beyond the photoresponse range of Si-based devices. It is also found that the PdSe₂ /pyramid Si heterojunction device can also function as an NIR light sensor, which can readily record both "tree" and "house" images produced by 980 and 1300 nm illumination, respectively.

Contact Engineering High-Performance n-Type MoTe2 Transistors

Semiconducting MoTe₂ is one of the few two-dimensional (2D) materials with a moderate band gap, similar to silicon. However, this material remains underexplored for 2D electronics due to ambient instability and predominantly p-type Fermi level pinning at contacts. Here, we demonstrate unipolar n-type MoTe₂ transistors with the highest performance to date, including high saturation current (>400 μA/μm at 80 K and >200 μA/μm at 300 K) and relatively low contact resistance (1.2 to 2 kΩ·μm from 80 to 300 K), achieved with Ag contacts and AlO_x encapsulation. We also investigate other contact metals (Sc, Ti, Cr, Au, Ni, Pt), extracting their Schottky barrier heights using an analytic subthreshold model. High-resolution X-ray photoelectron spectroscopy reveals that interfacial metal-Te compounds dominate the contact resistance. Among the metals studied, Sc has the lowest work function but is the most reactive, which we counter by inserting monolayer hexagonal boron nitride between MoTe₂ and Sc. These metal-insulator-semiconductor (MIS) contacts partly depin the metal Fermi level and lead to the smallest Schottky barrier for electron injection. Overall, this work improves our understanding of n-type contacts to 2D materials, an important advance for low-power electronics.

Electron Transport through Metal/MoS2 Interfaces: Edge- or Area-Dependent Process?

In ultrathin two-dimensional (2-D) materials, the formation of ohmic contacts with top metallic layers is a challenging task that involves different processes than in bulk-like structures. Besides the Schottky barrier height, the transfer length of electrons between metals and 2-D monolayers is a highly relevant parameter. For MoS₂, both short (≤30 nm) and long (≥0.5 μm) values have been reported, corresponding to either an abrupt carrier injection at the contact edge or a more gradual transfer of electrons over a large contact area. Here we use ab initio quantum transport simulations to demonstrate that the presence of an oxide layer between a metallic contact and a MoS₂ monolayer, for example, TiO₂ in the case of titanium electrodes, favors an area-dependent process with a long transfer length, while a perfectly clean metal-semiconductor interface would lead to an edge process. These findings reconcile several theories that have been postulated about the physics of metal/MoS₂ interfaces and provide a framework to design future devices with lower contact resistances.