Solution-Processed Self-Assembled Nanodielectrics on Template-Stripped Metal Substrates

A Sub-20 nm Organic/Inorganic Hybrid Dielectric for Ultralow-Power Organic Thin-Film Transistor (OTFT) With Enhanced Operational Stability

Organic/inorganic hybrid materials are utilized extensively as gate dielectric layers in organic thin-film transistors (OTFTs). However, inherently low dielectric constant of organic materials and lack of a reliable deposition process for organic layers hamper the broad application of hybrid dielectric materials. Here, a universal strategy to synthesize high-k hybrid dielectric materials by incorporating a high-k polymer layer on top of various inorganic layers generated by different fabrication methods, including AlO_x and HfO_x , is presented. Those hybrid dielectrics commonly exhibit high capacitance (>300 nF·cm^-2 ) as well as excellent insulating properties. A vapor-phase deposition method is employed for precise control of the polymer film thickness. The ultralow-voltage (<3 V) OTFTs are demonstrated based on the hybrid dielectric layer with 100% yield and uniform electrical characteristics. Moreover, the exceptionally high stability of OTFTs for long-term operation (current change less than 5% even under 30 h of voltage stress at 2.0 MV·cm^-1 ) is achieved. The hybrid dielectric is fully compatible with various substrates, which allows for the demonstration of intrinsically flexible OTFTs on the plastic substrate. It is believed that this approach for fabricating hybrid dielectrics by introducing the high-k organic material can be a promising strategy for future low-power, flexible electronics.

Self-Hybridized Exciton-Polaritons in Sub-10-nm-Thick WS2 Flakes: Roles of Optical Phase Shifts at WS2/Au Interfaces

Exciton–polaritons (EPs) can be formed in transition metal dichalcogenide (TMD) multilayers sustaining optical resonance modes without any external cavity. The self-hybridized EP modes are expected to depend on the TMD thickness, which directly determines the resonance wavelength. Exfoliated WS₂ flakes were prepared on SiO₂/Si substrates and template-stripped ultraflat Au layers, and the thickness dependence of their EP modes was compared. For WS₂ flakes on SiO₂/Si, the minimum flake thickness to exhibit exciton–photon anticrossing was larger than 40 nm. However, for WS₂ flakes on Au, EP mode splitting appeared in flakes thinner than 10 nm. Analytical and numerical calculations were performed to explain the distinct thickness-dependence. The phase shifts of light at the WS₂/Au interface, originating from the complex Fresnel coefficients, were as large as π/2 at visible wavelengths. Such exceptionally large phase shifts allowed the optical resonance and resulting EP modes in the sub-10-nm-thick WS₂ flakes. This work helps us to propose novel optoelectronic devices based on the intriguing exciton physics of TMDs.

Self-Assembled Nanodielectrics for Solution-Processed Top-Gate Amorphous IGZO Thin-Film Transistors

Metal oxide semiconductors, such as amorphous indium gallium zinc oxide (a-IGZO), have made impressive strides as alternatives to amorphous silicon for electronics applications. However, to achieve the full potential of these semiconductors, compatible unconventional gate dielectric materials must also be developed. To this end, solution-processable self-assembled nanodielectrics (SANDs) composed of structurally well-defined and durable nanoscopic alternating organic (e.g., stilbazolium) and inorganic oxide (e.g., ZrO_x and HfO_x) layers offer impressive capacitances and low processing temperatures (T ≤ 200 °C). While SANDs have been paired with diverse semiconductors and have yielded excellent device metrics, they have never been implemented in the most technologically relevant top-gate thin-film transistor (TFT) architecture. Here, we combine solution-processed a-IGZO with solution-processed four-layer Hf-SAND to fabricate top-gate TFTs, which exhibit impressive electron mobilities (μ_SAT = 19.4 cm² V^-1 s^-1) and low threshold voltages (V_th = 0.83 V), subthreshold slopes (SS = 293 mV/dec), and gate leakage currents (10^-10 A) as well as high bias stress stability.

Cross-Plane Thermal Conductance of Phosphonate-Based Self-Assembled Monolayers and Self-Assembled Nanodielectrics

Self-assembled nanodielectrics (SANDs) consist of alternating layers of polarized phosphonate-functionalized azastibazolium π-electron (PAE) and high-k dielectric metal oxide (ZrO₂ or HfO_x) films. SANDs are desirable gate dielectrics materials for thin-film transistor applications because of their excellent properties such as low-temperature fabrication, large dielectric strength, and large capacitance. In this paper, we investigate the cross-plane thermal boundary conductance of SANDs using the frequency domain thermoreflectance (FDTR) technique. First, we characterize the thermal conductance of PAE self-assembled monolayers (SAMs), inverted-PAE (IPAE) SAMs, and mixed PAE-IPAE SAMs, sandwiched between thin gold and silica (SiO₂) films at the top and bottom surfaces. Next, we quantify the thermal conductance of SAND-n with different numbers (n) of PAE-ZrO₂ layers and thicknesses ranging between 4.7 and 11.3 nm. From the FDTR measurements, we observe that the thermal boundary conductance of the SAMs can be tuned between 42.1 ± 4.6 MW/(m² K) and 52.4 ± 2.5 MW/(m² K), based on the relative density of the PAE and IPAE chromophores. In the SAND-n samples, we observe a monotonic decrease in the thermal conductance with increasing n. We use the measured thermal conductance data in a series resistance model to estimate a thermal interface conductance of 695 MW/(m² K) for the contact between the PAE chromophore and the zirconium dioxide films, which is an order of magnitude larger than the SAMs. We attribute the improved thermal conductance to stronger adhesion between the PAE chromophore and the zirconium dioxide films, as compared to the weakly bonded SAMs to the gold and silicon dioxide films.

Dry Transfer of van der Waals Crystals to Noble Metal Surfaces To Enable Characterization of Buried Interfaces

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) have been explored for many optoelectronic applications. Most of these applications require them to be on insulating substrates. However, for many fundamental property characterizations, such as mapping surface potential or conductance, insulating substrates are nonideal as they lead to charging and doping effects or impose the inhomogeneity of their charge environment on the atomically thin 2D layers. Here, we report a simple method of residue-free dry transfer of 2D TMDC crystal layers. This method is enabled via noble-metal (gold, silver) thin films and allows comprehensive nanoscale characterization of transferred TMDC crystals with multiple scanning probe microscopy techniques. In particular, intimate contact with underlying metal allows efficient tip-enhanced Raman scattering characterization, providing high spatial resolution (<20 nm) for Raman spectroscopy. Further, scanning Kelvin probe force microscopy allows high-resolution mapping of surface potential on transferred crystals, revealing their spatially varying structural and electronic properties. The layer-dependent contact potential difference is clearly observed and explained by charge transfer from contacts with Au and Ag. The demonstrated sample preparation technique can be generalized to probe many different 2D material surfaces and has broad implications in understanding of the metal contacts and buried interfaces in 2D material-based devices.

Solution Processed Metal Oxide High-κ Dielectrics for Emerging Transistors and Circuits

The electronic functionalities of metal oxides comprise conductors, semiconductors, and insulators. Metal oxides have attracted great interest for construction of large-area electronics, particularly thin-film transistors (TFTs), for their high optical transparency, excellent chemical and thermal stability, and mechanical tolerance. High-permittivity (κ) oxide dielectrics are a key component for achieving low-voltage and high-performance TFTs. With the expanding integration of complementary metal oxide semiconductor transistors, the replacement of SiO2 with high-κ oxide dielectrics has become urgently required, because their provided thicker layers suppress quantum mechanical tunneling. Toward low-cost devices, tremendous efforts have been devoted to vacuum-free, solution processable fabrication, such as spin coating, spray pyrolysis, and printing techniques. This review focuses on recent progress in solution processed high-κ oxide dielectrics and their applications to emerging TFTs. First, the history, basics, theories, and leakage current mechanisms of high-κ oxide dielectrics are presented, and the underlying mechanism for mobility enhancement over conventional SiO2 is outlined. Recent achievements of solution-processed high-κ oxide materials and their applications in TFTs are summarized and traditional coating methods and emerging printing techniques are introduced. Finally, low temperature approaches, e.g., ecofriendly water-induced, self-combustion reaction, and energy-assisted post treatments, for the realization of flexible electronics and circuits are discussed.

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

Inhibiting Metal Oxide Atomic Layer Deposition: Beyond Zinc Oxide

Atomic layer deposition (ALD) of several metal oxides is selectivity inhibited on alkanethiol self-assembled monolayers (SAMs) on Au, and the eventual nucleation mechanism is investigated. The inhibition ability of the SAM is significantly improved by the in situ H₂-plasma pretreatment of the Au substrate prior to the gas-phase deposition of a long-chain alkanethiol, 1-dodecanethiol (DDT). This more rigorous surface preparation inhibits even aggressive oxide ALD precursors, including trimethylaluminum and water, for at least 20 cycles. We study the effect that the ALD precursor purge times, growth temperature, alkanethiol chain length, alkanethiol deposition time, and plasma treatment time have on Al₂O₃ ALD inhibition. This is the first example of Al₂O₃ ALD inhibition from a vapor-deposited SAM. The inhibitions of Al₂O₃, ZnO, and MnO ALD processes are compared, revealing the versatility of this selective surface treatment. Atomic force microscopy and grazing-incidence X-ray fluorescence further reveal insight into the mechanism by which the well-defined surface chemistry of ALD may eventually be circumvented to allow metal oxide nucleation and growth on SAM-modified surfaces.

High Photovoltaic Quantum Efficiency in Ultrathin van der Waals Heterostructures

We report experimental measurements for ultrathin (<15 nm) van der Waals heterostructures exhibiting external quantum efficiencies exceeding 50% and show that these structures can achieve experimental absorbance >90%. By coupling electromagnetic simulations and experimental measurements, we show that pn WSe₂/MoS₂ heterojunctions with vertical carrier collection can have internal photocarrier collection efficiencies exceeding 70%.

Near-Unity Absorption in van der Waals Semiconductors for Ultrathin Optoelectronics

We demonstrate near-unity, broadband absorbing optoelectronic devices using sub-15 nm thick transition metal dichalcogenides (TMDCs) of molybdenum and tungsten as van der Waals semiconductor active layers. Specifically, we report that near-unity light absorption is possible in extremely thin (<15 nm) van der Waals semiconductor structures by coupling to strongly damped optical modes of semiconductor/metal heterostructures. We further fabricate Schottky junction devices using these highly absorbing heterostructures and characterize their optoelectronic performance. Our work addresses one of the key criteria to enable TMDCs as potential candidates to achieve high optoelectronic efficiency.