Mobility Deception in Nanoscale Transistors: An Untold Contact Story

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Silicon transistors are approaching their physical limit, calling for the emergence of a technological revolution. As the acknowledged ultimate version of transistor channels, 2D semiconductors are of interest for the development of post-Moore electronics due to their useful properties and all-in-one potentials. Here, the promise and current status of 2D semiconductors and transistors are reviewed, from materials and devices to integrated applications. First, we outline the evolution and challenges of silicon-based integrated circuits, followed by a detailed discussion on the properties and preparation strategies of 2D semiconductors and van der Waals heterostructures. Subsequently, the significant progress of 2D transistors, including device optimization, large-scale integration, and unconventional devices, are presented. We also examine 2D semiconductors for advanced heterogeneous and multifunctional integration beyond CMOS. Finally, the key technical challenges and potential strategies for 2D transistors and integrated circuits are also discussed. We envision that the field of 2D semiconductors and transistors could yield substantial progress in the upcoming years and hope this review will trigger the interest of scientists planning their next experiment.

Physical vapor deposition-free scalable high-efficiency electrical contacts to MoS2

Fermi-level pinning caused by the kinetic damage during metallization has been recognized as one of the major reasons for the non-ideal behavior of electrical contacts, forbidding reaching the Schottky-Mott limit. In this manuscript, we present a scalable technique wherein Indium, a low-work-function metal, is diffused to contact a few-layered MoS2flake. The technique exploits a smooth outflow of Indium over gold electrodes to make edge contacts to pre-transferred MoS2flakes. We compare the performance of three pairs of contacts made onto the same MoS2flake, the bottom-gold, top-gold, and Indium contacts, and find that the Indium contacts are superior to other contacts. The Indium contacts maintain linearI-Vcharacteristics down to cryogenic temperatures with an extracted Schottky barrier height of ∼2.1 meV. First-principle calculations show the induced in-gap states close to the Fermi level, and the damage-free contact interface could be the reason for the nearly Ohmic behavior of the Indium/MoS2interface.

Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping

n-type field effect transistors (FETs) based on two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2 and WS2 have come close to meeting the requirements set forth in the International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance standards. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high performance p-type FETs based on synthetic WSe2. Using electrical measurements backed by atomistic imaging and rigorous analysis, Pd was identified as the favorable contact metal for WSe2 owing to better epitaxy, larger grain size, and higher compressive strain, leading to a lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ∼10× by aggressively scaling Lch from 1 μm down to ∼20 nm, ultrascaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidation of bilayer WSe2 was used as a p-type dopant. This led to ∼5× improvement in the ON-state performance and ∼9× reduction in the contact resistance. We were able to achieve a median ON-state current as high as ∼10 μA/μm for ultrascaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials such as MoS2, MoTe2, and MoSe2.

Thermally Driven Multilevel Non-Volatile Memory with Monolayer MoS2 for Brain-Inspired Artificial Learning

The demands of modern electronic components require advanced computing platforms for efficient information processing to realize in-memory operations with a high density of data storage capabilities toward developing alternatives to von Neumann architectures. Herein, we demonstrate the multifunctionality of monolayer MoS₂ memtransistors, which can be used as a high-geared intrinsic transistor at room temperature; however, at a high temperature (>350 K), they exhibit synaptic multilevel memory operations. The temperature-dependent memory mechanism is governed by interfacial physics, which solely depends on the gate field modulated ion dynamics and charge transfer at the MoS₂/dielectric interface. We have proposed a non-volatile memory application using a single Field Effect Transistor (FET) device where thermal energy can be ventured to aid the memory functions with multilevel (3-bit) storage capabilities. Furthermore, our devices exhibit linear and symmetry in conductance weight updates when subjected to electrical potentiation and depression. This feature has enabled us to attain a high classification accuracy while training and testing the Modified National Institute of Standards and Technology datasets through artificial neural network simulation. This work paves the way toward reliable data processing and storage using 2D semiconductors with high-packing density arrays for brain-inspired artificial learning.

Ultrascaled Contacts to Monolayer MoS2 Field Effect Transistors

Two-dimensional (2D) semiconductors possess promise for the development of field-effect transistors (FETs) at the ultimate scaling limit due to their strong gate electrostatics. However, proper FET scaling requires reduction of both channel length (L_CH) and contact length (L_C), the latter of which has remained a challenge due to increased current crowding at the nanoscale. Here, we investigate Au contacts to monolayer MoS₂ FETs with L_CH down to 100 nm and L_C down to 20 nm to evaluate the impact of contact scaling on FET performance. Au contacts are found to display a ∼2.5× reduction in the ON-current, from 519 to 206 μA/μm, when L_C is scaled from 300 to 20 nm. It is our belief that this study is warranted to ensure an accurate representation of contact effects at and beyond the technology nodes currently occupied by silicon.

Scaling of MoS2 Transistors and Inverters to Sub-10 nm Channel Length with High Performance

Two-dimensional (2D) semiconductors such as monolayer molybdenum disulfide (MoS₂) are promising building blocks for ultrascaled field effect transistors (FETs), benefiting from their atomic thickness, dangling-bond-free flat surface, and excellent gate controllability. However, despite great prospects, the fabrication of 2D ultrashort channel FETs with high performance and uniformity remains a challenge. Here, we report a self-encapsulated heterostructure undercut technique for the fabrication of sub-10 nm channel length MoS₂ FETs. The fabricated 9 nm channel MoS₂ FETs exhibit superior performances compared with sub-15 nm channel length including the competitive on-state current density of 734/433 μA/μm at V_DS = 2/1 V, record-low DIBL of ∼50 mV/V, and superior on/off ratio of 3 × 10⁷ and low subthreshold swing of ∼100 mV/dec. Furthermore, the ultrashort channel MoS₂ FETs fabricated by this new technique show excellent homogeneity. Thanks to this, we scale the monolayer inverter down to sub-10 nm channel length.

Edge and Interface Resistances Create Distinct Trade-Offs When Optimizing the Microstructure of Printed van der Waals Thin-Film Transistors

Inks based on two-dimensional (2D) materials could be used to tune the properties of printed electronics while maintaining compatibility with scalable manufacturing processes. However, a very wide range of performances have been reported in printed thin-film transistors in which the 2D channel material exhibits considerable variation in microstructure. The lack of quantitative physics-based relationships between film microstructure and transistor performance limits the codesign of exfoliation, sorting, and printing processes to inefficient empirical approaches. To rationally guide the development of 2D inks and related processing, we report a gate-dependent resistor network model that establishes distinct microstructure-performance relationships created by near-edge and intersheet resistances in printed van der Waals thin-film transistors. The model is calibrated by analyzing electrical output characteristics of model transistors consisting of overlapping 2D nanosheets with varied thicknesses that are mechanically exfoliated and transferred. Kelvin probe force microscopy analysis on the model transistors leads to the discovery that the nanosheet edges, not the intersheet resistance, limit transport due to their impact on charge carrier depletion and scattering. Our model suggests that when transport in a 2D material network is limited by the near-edge resistance, the optimum nanosheet thickness is dictated by a trade-off between charged impurity screening and gate screening, and the film mobilities are more sensitive to variations in printed nanosheet density. Removal of edge states can enable the realization of higher mobilities with thinner nanosheets due to reduced junction resistances and reduced gate screening. Our analysis of the influence of nanosheet edges on the effective film mobility not only examines the prospects of extant exfoliation methods to achieve the optimum microstructure but also provides important perspectives on processes that are essential to maximizing printed film performance.

The Road for 2D Semiconductors in the Silicon Age

Continued reduction in transistor size can improve the performance of silicon integrated circuits (ICs). However, as Moore's law approaches physical limits, high-performance growth in silicon ICs becomes unsustainable, due to challenges of scaling, energy efficiency, and memory limitations. The ultrathin layers, diverse band structures, unique electronic properties, and silicon-compatible processes of 2D materials create the potential to consistently drive advanced performance in ICs. Here, the potential of fusing 2D materials with silicon ICs to minimize the challenges in silicon ICs, and to create technologies beyond the von Neumann architecture, is presented, and the killer applications for 2D materials in logic and memory devices to ease scaling, energy efficiency bottlenecks, and memory dilemmas encountered in silicon ICs are discussed. The fusion of 2D materials allows the creation of all-in-one perception, memory, and computation technologies beyond the von Neumann architecture to enhance system efficiency and remove computing power bottlenecks. Progress on the 2D ICs demonstration is summarized, as well as the technical hurdles it faces in terms of wafer-scale heterostructure growth, transfer, and compatible integration with silicon ICs. Finally, the promising pathways and obstacles to the technological advances in ICs due to the integration of 2D materials with silicon are presented.

Optically Modulated HfS2-Based Synapses for Artificial Vision Systems

The simulation of human brain neurons by synaptic devices could be an effective strategy to break through the notorious "von Neumann Bottleneck" and "Memory Wall". Herein, opto-electronic synapses based on layered hafnium disulfide (HfS₂) transistors have been investigated. The basic functions of biological synapses are realized and optimized by modifying pulsed light conditions. Furthermore, 2 × 2 pixel imaging chips have also been developed. Two-pixel visual information is illuminated on diagonal pixels of the imaging array by applying light pulses (λ = 405 nm) with different pulse frequencies, mimicking short-term memory and long-term memory characteristics of the human vision system. In addition, an optically/electrically driven neuromorphic computation is demonstrated by machine learning to classify hand-written numbers with an accuracy of about 88.5%. This work will be an important step toward an artificial neural network comprising neuromorphic vision sensing and training functions.

Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS2

Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS₂ films at 560 °C in 50 min, within the 450-to-600 °C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ∼140 μA/μm at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS₂ grown below 600 °C using solid-source precursors. The effective mobility from transfer length method test structures is 29 ± 5 cm² V^-1 s^-1 at 6.1 × 10¹² cm^-2 electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.

Mobility Extraction in 2D Transition Metal Dichalcogenide Devices-Avoiding Contact Resistance Implicated Overestimation

Schottky barrier (SB) transistors operate distinctly different from conventional metal-oxide semiconductor field-effect transistors, in a unique way that the gate impacts the carrier injection from the metal source/drain contacts into the channel region. While it has been long recognized that this can have severe implications for device characteristics in the subthreshold region, impacts of contact gating of SB in the on-state of the devices, which affects evaluation of intrinsic channel properties, have been yet comprehensively studied. Due to the fact that contact resistance (R_C ) is always gate-dependent in a typical back-gated device structure, the traditional approach of deriving field-effect mobility from the maximum transconductance (g_m ) is in principle not correct and can even overestimate the mobility. In addition, an exhibition of two different threshold voltages for the channel and the contact region leads to another layer of complexity in determining the true carrier concentration calculated from Q = C_OX * (V_G -V_TH ). Through a detailed experimental analysis, the effect of different effective oxide thicknesses, distinct SB heights, and doping-induced reductions in the SB width are carefully evaluated to gain a better understanding of their impact on important device metrics.

Double-Gate MoS2 Field-Effect Transistors with Full-Range Tunable Threshold Voltage for Multifunctional Logic Circuits

Multifunctional reconfigurable devices, with higher information capacity, smaller size, and more functions, are urgently needed and draw most attention in frontiers in information technology. 2D semiconductors, ascribing to ultrathin body and easy electrostatic control, show great potential in developing reconfigurable functional units. This work proposes a novel double-gate field-effect transistor architecture with equal top and bottom gate (TG and BG) and realizes flexible optimization of the subthreshold swing (SS) and threshold voltage (V_TH ). While the TG and BG are used simultaneously, as a single gate to drive the transistor, ultralow average SS value of 65.5 mV dec^-1 can be obtained in a large current range over 10⁴ , enabling the application in high gain inverter. While one gate is used to initialize the channel doping, full logic swing inverter circuit with high noise margin (over 90%) is demonstrated. Such device prototype is further extended for designing reconfigurable logic applications and can be dynamically switched and well maintained between binary and ternary logics. This study provides important concept and device prototype for future multifunctional logic applications.

Low-Temperature 2D/2D Ohmic Contacts in WSe2 Field-Effect Transistors as a Platform for the 2D Metal-Insulator Transition

We report the fabrication of hexagonal-boron-nitride (hBN) encapsulated multiterminal WSe₂ Hall bars with 2D/2D low-temperature Ohmic contacts as a platform for investigating the two-dimensional (2D) metal-insulator transition. We demonstrate that the WSe₂ devices exhibit Ohmic behavior down to 0.25 K and at low enough excitation voltages to avoid current-heating effects. Additionally, the high-quality hBN-encapsulated WSe₂ devices in ideal Hall-bar geometry enable us to accurately determine the carrier density. Measurements of the temperature (T) and density (n_s) dependence of the conductivity σ(T, n_s) demonstrate scaling behavior consistent with a metal-insulator quantum phase transition driven by electron-electron interactions but where disorder-induced local magnetic moments are also present. Our findings pave the way for further studies of the fundamental quantum mechanical properties of 2D transition metal dichalcogenides using the same contact engineering.

Promises and prospects of two-dimensional transistors

Two-dimensional (2D) semiconductors have attracted tremendous interest as atomically thin channels that could facilitate continued transistor scaling. However, despite many proof-of-concept demonstrations, the full potential of 2D transistors has yet to be determined. To this end, the fundamental merits and technological limits of 2D transistors need a critical assessment and objective projection. Here we review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking 2D transistors. We suggest that the saturation or on-state current density, especially in the short-channel limit, could provide a more reliable measure for assessing the potential of diverse 2D semiconductors, and should be applied for cross-checking different studies, especially when milestone performance metrics are claimed. We also summarize the key technical challenges in optimizing the channels, contacts, dielectrics and substrates and outline potential pathways to push the performance limit of 2D transistors. We conclude with an overview of the critical technical targets, the key technological obstacles to the 'lab-to-fab' transition and the potential opportunities arising from the use of these atomically thin semiconductors.

Benchmarking monolayer MoS2 and WS2 field-effect transistors

Here we benchmark device-to-device variation in field-effect transistors (FETs) based on monolayer MoS₂ and WS₂ films grown using metal-organic chemical vapor deposition process. Our study involves 230 MoS₂ FETs and 160 WS₂ FETs with channel lengths ranging from 5 μm down to 100 nm. We use statistical measures to evaluate key FET performance indicators for benchmarking these two-dimensional (2D) transition metal dichalcogenide (TMD) monolayers against existing literature as well as ultra-thin body Si FETs. Our results show consistent performance of 2D FETs across 1 × 1 cm² chips owing to high quality and uniform growth of these TMDs followed by clean transfer onto device substrates. We are able to demonstrate record high carrier mobility of 33 cm² V^-1 s^-1 in WS₂ FETs, which is a 1.5X improvement compared to the best reported in the literature. Our experimental demonstrations confirm the technological viability of 2D FETs in future integrated circuits.

Schottky barrier lowering due to interface states in 2D heterophase devices

The Schottky barrier of a metal-semiconductor junction is one of the key quantities affecting the charge transport in a transistor. The Schottky barrier height depends on several factors, such as work function difference, local atomic configuration in the interface, and impurity doping. We show that also the presence of interface states at 2D metal-semiconductor junctions can give rise to a large renormalization of the effective Schottky barrier determined from the temperature dependence of the current. We investigate the charge transport in n- and p-doped monolayer MoTe₂ 1T'-1H junctions using ab initio quantum transport calculations. The Schottky barriers are extracted both from the projected density of states and the transmission spectrum, and by simulating the IT-characteristic and applying the thermionic emission model. We find interface states originating from the metallic 1T' phase rather than the semiconducting 1H phase in contrast to the phenomenon of Fermi level pinning. Furthermore, we find that these interface states mediate large tunneling currents which dominates the charge transport and can lower the effective barrier to a value of only 55 meV.

Contact and injection engineering for low SS reconfigurable FETs and high gain complementary inverters

The newly emerged two-dimensional (2D) semiconducting materials, owning to the atomic thick nature and excellent optical and electrical properties, are considered as potential candidates to solve the bottlenecks of traditional semiconductors. However, the realization of high performance 2D semiconductor-based field-effect transistors (FETs) has been a longstanding challenge in 2D electronics, which is mainly ascribing to the presence of significant Schottky barrier (SB) at metal-semiconductor interfaces. Here, an additional contact gate is induced in 2D ambipolar FET to realize near ideal reconfigurable FET (RFET) devices without restrictions of SB. Benefitting from the consistently high doping of contact region, the effective SB height can be maintained at ultra-small value during all operation conditions, resulting in the near ideal subthreshold swing (SS) values (132 mV/decade for MoTe₂ RFET and 67 mV/decade for WSe₂ RFET) and the relatively high mobility (28.6 cm²/(V s) for MoTe₂ RFET and 89.8 cm²/(V s) for WSe₂ RFET). Moreover, the flexible control on the doping polarity of contact region enables the remodeling and switching of the achieved unipolar FETs between p-type mode and n-type mode. Based on such reconfigurable behaviors, high gain complementary MoTe₂ inverters are further realized. The findings in this work push forward the development of high-performance 2D semiconductor integrated devices and circuits.

Scalable Substitutional Re-Doping and its Impact on the Optical and Electronic Properties of Tungsten Diselenide

Reliable, controlled doping of 2D transition metal dichalcogenides will enable the realization of next-generation electronic, logic-memory, and magnetic devices based on these materials. However, to date, accurate control over dopant concentration and scalability of the process remains a challenge. Here, a systematic study of scalable in situ doping of fully coalesced 2D WSe₂ films with Re atoms via metal-organic chemical vapor deposition is reported. Dopant concentrations are uniformly distributed over the substrate surface, with precisely controlled concentrations down to <0.001% Re achieved by tuning the precursor partial pressure. Moreover, the impact of doping on morphological, chemical, optical, and electronic properties of WSe₂ is elucidated with detailed experimental and theoretical examinations, confirming that the substitutional doping of Re at the W site leads to n-type behavior of WSe₂ . Transport characteristics of fabricated back-gated field-effect-transistors are directly correlated to the dopant concentration, with degrading device performances for doping concentrations exceeding 1% of Re. The study demonstrates a viable approach to introducing true dopant-level impurities with high precision, which can be scaled up to batch production for applications beyond digital electronics.

In Situ Study of Molecular Doping of Chlorine on MoS2 Field Effect Transistor Device in Ultrahigh Vacuum Conditions

We report a precise measurement of the sensor behavior of the field effect transistor (FET) formed with the MoS₂ channel when the channel part is exposed to Cl₂ gas. The gas exposure and the electrical measurement of the MoS₂ FET were executed with in situ ultrahigh-vacuum (UHV) conditions in which the surface analysis techniques were equipped. This makes it possible to detect how much sensitivity the MoS₂ FET can provide and understand the surface properties. With the Cl₂ gas exposure to the channel, the plot of the drain current versus the gate voltage (I _d-V _g curve) shifts monotonically toward the positive direction of V _g, suggesting that the adsorbate acts as an electron acceptor. The I _d-V _g shifts are numerically estimated by measuring the onset of I _d (threshold voltage, V _th) and the mobility as a function of the dosing amounts of the Cl₂ gas. The behaviors of both the V _th shift and the mobility with the Cl₂ dosing amount can be fitted with the Langmuir adsorption kinetics, which is typically seen in the uptake curve of molecule adsorption onto well-defined surfaces. This can be accounted for by a model where an impinging molecule occupies an empty site with a certain probability, and each adsorbate receives a certain amount of negative charge from the MoS₂ surface up to the monolayer coverage. The charge transfer makes the V _th shifts. In addition, the mobility is reduced by the enhancement of the Coulomb scattering for the electron flow in the MoS₂ channel by the accumulated charge. From the thermal desorption spectroscopy (TDS) measurement and density functional theory (DFT) calculations, we concluded that the adsorbate that is responsible for the change of the FET property is the Cl atom that is dissociated from the Cl₂ molecule. The monotonic shift of V _th with the coverage suggests that the MoS₂ device sensor has a good sensitivity to detect 10^-3 monolayers (ML) of adsorption corresponding to the ppb level sensor with an activation time of 1 s.

Stochastic resonance in MoS2 photodetector

In this article, we adopt a radical approach for next generation ultra-low-power sensor design by embracing the evolutionary success of animals with extraordinary sensory information processing capabilities that allow them to survive in extreme and resource constrained environments. Stochastic resonance (SR) is one of those astounding phenomena, where noise, which is considered detrimental for electronic circuits and communication systems, plays a constructive role in the detection of weak signals. Here, we show SR in a photodetector based on monolayer MoS₂ for detecting ultra-low-intensity subthreshold optical signals from a distant light emitting diode (LED). We demonstrate that weak periodic LED signals, which are otherwise undetectable, can be detected by a MoS₂ photodetector in the presence of a finite and optimum amount of white Gaussian noise at a frugal energy expenditure of few tens of nano-Joules. The concept of SR is generic in nature and can be extended beyond photodetector to any other sensors.

Here, the authors take advantage of stochastic resonance in a photodetector based on monolayer MoS₂ for measuring otherwise undetectable, ultra-low-intensity, subthreshold optical signals from a distant light emitting diode in the presence of a finite and optimum amount of white Gaussian noise.

Native Oxide Seeded Spontaneous Integration of Dielectrics on Exfoliated Black Phosphorus

Two-dimensional (2D) semiconductors have been a central focus for next-generation electronics and optoelectronics owing to their great potential to extend the scaling limits in a silicon transistor. However, due to the lack of surface dangling bonds in most 2D semiconductors, such as graphene and transition metal dichalcogenides (TMDs), the direct growth of the high-κ film on these 2D materials via an atomic layer deposition (ALD) technique often produces dielectrics with poor quality, which hinders their integration in the modern semiconductor industry. Here, we comprehensively investigate the ALD growth of the Al₂O₃ layer on 2D exfoliated black phosphorus (BP). Intriguingly, we found that the 2D BP with "silicon-like" characteristics possesses a native surface oxide layer P_xO_y after air exposure. The P_xO_y-induced surface dangling bonds enable the spontaneous integration of the high-quality Al₂O₃ layer on the BP flake without any pretreatments to functionalize the surface. Additionally, the Al₂O₃ layer could effectively passivate BP to prevent its degradation in ambient conditions, which addresses the most serious problem of the BP material. Moreover, the Al₂O₃-encapsulated BP field-effect transistor (FET) exhibits good electrical transport performance, with a high hole mobility of ∼420 cm² V^-1 s^-1 and electron mobility of ∼80 cm² V^-1 s^-1. Moreover, the high-quality Al₂O₃ layer can also be integrated into the top-gated BP transistor and inverter. Our findings reveal the silicon-like characteristics of BP for the high-κ ALD dielectric growth technology, which promises the seamless integration of 2D BP in the modern semiconductor industry.

Wafer-Scale, Conformal, and Low-Temperature Synthesis of Layered Tin Disulfides for Emerging Nonplanar and Flexible Electronics

Two-dimensional (2D) metal dichalcogenides have drawn considerable interest because they offer possibilities for the implementation of emerging electronics. The emerging electronics are moving toward two major directions: vertical expansion of device space and flexibility. However, the development of a synthesis method for 2D metal dichalcogenides that meets all the requirements remains a significant challenge. Here, we propose a promising method for wafer-scale, conformal, and low-temperature (≤240 °C) synthesis of single-phase SnS₂ via the atomic layer deposition technique. There is a trade-off relationship between the crystallinity and orientation preference of SnS₂, which is efficiently eliminated by the two-step growth occurring at different temperatures. Consequently, the van der Waals layers of the highly crystalline SnS₂ are parallel to the substrate. Thin-film transistors (TFTs) comprising the SnS₂ layer show reasonable electrical performances (field-effect mobility: ∼0.8 cm² V^-1 s^-1 and on/off ratio: ∼10⁶), which are comparable to that of a single-crystal SnS₂ flake. Moreover, we demonstrate nonplanar and flexible TFTs to identify the feasibility of the implementation of future electronics. Both the diagonal-structured TFT and flexible TFT fabricated without a transfer process show electrical performances comparable to those of rigid and planar TFTs. Particularly, the flexible TFT does not exhibit substantial degradation even after 2000 bending cycles. Our work would provide decisive opportunities for the implementation of future electronic devices utilizing 2D metal chalcogenides.

Gaussian synapses for probabilistic neural networks

The recent decline in energy, size and complexity scaling of traditional von Neumann architecture has resurrected considerable interest in brain-inspired computing. Artificial neural networks (ANNs) based on emerging devices, such as memristors, achieve brain-like computing but lack energy-efficiency. Furthermore, slow learning, incremental adaptation, and false convergence are unresolved challenges for ANNs. In this article we, therefore, introduce Gaussian synapses based on heterostructures of atomically thin two-dimensional (2D) layered materials, namely molybdenum disulfide and black phosphorus field effect transistors (FETs), as a class of analog and probabilistic computational primitives for hardware implementation of statistical neural networks. We also demonstrate complete tunability of amplitude, mean and standard deviation of the Gaussian synapse via threshold engineering in dual gated molybdenum disulfide and black phosphorus FETs. Finally, we show simulation results for classification of brainwaves using Gaussian synapse based probabilistic neural networks.

Immunity to Contact Scaling in MoS2 Transistors Using in Situ Edge Contacts

Atomically thin two-dimensional (2D) materials are promising candidates for sub-10 nm transistor channels due to their ultrathin body thickness, which results in strong electrostatic gate control. Properly scaling a transistor technology requires reducing both the channel length (distance from source to drain) and the contact length (distance that source and drain interface with semiconducting channel). Contact length scaling remains an unresolved epidemic for transistor scaling, affecting devices from all semiconductors-silicon to 2D materials. Here, we show that clean edge contacts to 2D MoS₂ can provide immunity to the contact-scaling problem, with performance that is independent of contact length down to the 20 nm regime. Using a directional ion beam, in situ edge contacts of various metal-MoS₂ interfaces are studied. Characterization of the intricate edge interface using cross-sectional electron microscopy reveals distinct morphological effects on the MoS₂ depending on its thickness-from monolayer to few-layer films. The in situ edge contacts also exhibit an order of magnitude higher performance compared to the best-reported ex situ metal edge contacts. Our work provides experimental evidence for a solution to contact scaling in transistors, using 2D materials with clean edge contact interfaces, opening a new way of designing devices with 2D materials.

Defect-Controlled Nucleation and Orientation of WSe2 on hBN: A Route to Single-Crystal Epitaxial Monolayers

A defect-controlled approach for the nucleation and epitaxial growth of WSe₂ on hBN is demonstrated. The WSe₂ domains exhibit a preferred orientation of over 95%, leading to a reduced density of inversion domain boundaries (IDBs) upon coalescence. First-principles calculations and experimental studies as a function of growth conditions and substrate pretreatment confirm that WSe₂ nucleation density and orientation are controlled by the hBN surface defect density rather than thermodynamic factors. Detailed transmission electron microscopy analysis provides support for the role of single-atom vacancies on the hBN surface that trap W atoms and break surface symmetry leading to a reduced formation energy for one orientation of WSe₂ domains. Through careful control of nucleation and extended lateral growth time, fully coalesced WSe₂ monolayer films on hBN were achieved. Low-temperature photoluminescence (PL) measurements and transport measurements of back-gated field-effect transistor devices fabricated on WSe₂/hBN films show improved optical and electrical properties compared to films grown on sapphire under similar conditions. Our results reveal an important nucleation mechanism for the epitaxial growth of van der Waals heterostructures and demonstrate hBN as a superior substrate for single-crystal transition-metal dichalcogenide (TMD) films, resulting in a reduced density of IDBs and improved properties. The results motivate further efforts focused on the development of single crystal hBN substrates and epilayers for synthesis of wafer-scale single crystal TMD films.