III-V Integration on Si(100): Vertical Nanospades

Polarization Control in Integrated Silicon Waveguides Using Semiconductor Nanowires

In this work, we show the design of a silicon photonic-based polarization converting device based on the integration of semiconduction InP nanowires on the silicon photonic platform. We present a comprehensive numerical analysis showing that full polarization conversion (from quasi-TE modes to quasi-TM modes, and vice versa) can be achieved in devices exhibiting small footprints (total device lengths below 20 µm) with minimal power loss (<2 dB). The approach described in this work can pave the way to the realization of complex and re-configurable photonic processors based on the manipulation of the state of polarization of guided light beams.

Nanoscale Mapping of Light Emission in Nanospade-Based InGaAs Quantum Wells Integrated on Si(100): Implications for Dual Light-Emitting Devices

III-V semiconductors outperform Si in many optoelectronics applications due to their high carrier mobility, efficient light emission and absorption processes, and the possibility to engineer their band gap through alloying. However, complementing Si technology with III-V semiconductors by integration on Si(100) remains a challenge still today. Vertical nanospades (NSPDs) are quasi-bi-crystal III-V nanostructures that grow on Si(100). Here, we showcase the potential of these structures in optoelectronics application by demonstrating InGaAs heterostructures on GaAs NSPDs that exhibit bright emission in the near-infrared region. Using cathodoluminescence hyperspectral imaging, we are able to study light emission properties at a few nanometers of spatial resolution, well below the optical diffraction limit. We observe a symmetric spatial luminescence splitting throughout the NSPD. We correlate this characteristic to the structure's crystal nature, thus opening new perspectives for dual wavelength light-emitting diode structures. This work paves the path for integrating optically active III-V structures on the Si(100) platform.

1D Germanium Sulfide van der Waals Bicrystals by Vapor-Liquid-Solid Growth

Defects in two-dimensional and layered materials have attracted interest for realizing properties different from those of perfect crystals. Even stronger links between defect formation, fast growth, and emerging functionality can be found in nanostructures of van der Waals crystals, but only a few prevalent morphologies and defect-controlled synthesis processes have been identified. Here, we show that in vapor-liquid-solid growth of 1D van der Waals nanostructures, the catalyst controls the selection of the predominant (fast-growing) morphologies. Growth of layered GeS over Bi catalysts leads to two coexisting nanostructure types: chiral nanowires carrying axial screw dislocations and bicrystal nanoribbons where a central twin plane facilitates rapid growth. While Au catalysts produce exclusively dislocated nanowires, their modification with an additive triggers a switch to twinned bicrystal ribbons. Nanoscale spectroscopy shows that, while supporting fast growth, the twin defects in the distinctive layered bicrystals are electronically benign and free of nonradiative recombination centers.

Large-Scale Monolithic Fabrication of III-V Vertical Nanowires on a Standard Si(100) Microelectronic Substrate

Vertical III-V nanowires are of great interest for a large number of applications, but their integration still suffers from manufacturing difficulties of these one-dimensional nanostructures on the standard Si(100) microelectronic platform at a large scale. Here, a top-down approach based on the structure of a thin III-V epitaxial layer on Si was proposed to obtain monolithic GaAs or GaSb nanowires as well as GaAs-Si nanowires with an axial heterostructure. Based on a few complementary metal-oxide-semiconductor-compatible fabrication steps, III-V nanowires with a high crystalline quality as well as a uniform diameter (30 nm), morphology, positioning, and orientation were fabricated. In addition, the patterning control of nanowires at the nanoscale was thoroughly characterized by structural and chemical analyses to finely tune the key process parameters. To properly control the morphology of the nanowires during reactive-ion etching (RIE), the balance between the plasma properties and the formation of a protective layer on the nanowire sidewall was studied in detail. Furthermore, high-resolution microscopy analyses were performed to gain a better understanding of the protective layer's composition and to observe the crystalline quality of the nanowires. This approach paves the way for the possible scale-up integration of III-V-based nanowire devices with conventional Si/complementary metal-oxide-semiconductor technology.

GaAs nanowires on Si nanopillars: towards large scale, phase-engineered arrays

Large-scale patterning for vapor-liquid-solid growth of III-V nanowires is a challenge given the required feature size for patterning (45 to 60 nm holes). In fact, arrays are traditionally manufactured using electron-beam lithography,for which processing times increase greatly when expanding the exposure area. In order to bring nanowire arrays one step closer to the wafer-scale we take a different approach and replace patterned nanoscale holes with Si nanopillar arrays. The method is compatible with photolithography methods such as phase-shift lithography or deep ultraviolet (DUV) stepper lithography. We provide clear evidence on the advantage of using nanopillars as opposed to nanoscale holes both for the control on the growth mechanisms and for the scalability. We identify the engineering of the contact angle as the key parameter to optimize the yield. In particular, we demonstrate how nanopillar oxidation is key to stabilize the Ga catalyst droplet and engineer the contact angle. We demonstrate how the position of the triple phase line at the SiO₂/Si as opposed to the SiO₂/vacuum interface is central for a successful growth. We compare our experiments with simulations performed in surface evolver™ and observe a strong correlation. Large-scale arrays using phase-shift lithography result in a maximum local vertical yield of 67% and a global chip-scale yield of 40%. We believe that, through a greater control over key processing steps typically achieved in a semiconductor fab it is possible to push this yield to 90+% and open perspectives for deterministic nanowire phase engineering at the wafer-scale.

Understanding Shape Evolution and Phase Transition in InP Nanostructures Grown by Selective Area Epitaxy

There is a strong demand for III-V nanostructures of different geometries and in the form of interconnected networks for quantum science applications. This can be achieved by selective area epitaxy (SAE) but the understanding of crystal growth in these complicated geometries is still insufficient to engineer the desired shape. Here, the shape evolution and crystal structure of InP nanostructures grown by SAE on InP substrates of different orientations are investigated and a unified understanding to explain these observations is established. A strong correlation between growth direction and crystal phase is revealed. Wurtzite (WZ) and zinc-blende (ZB) phases form along <111>A and <111>B directions, respectively, while crystal phase remains the same along other low-index directions. The polarity induced crystal structure difference is explained by thermodynamic difference between the WZ and ZB phase nuclei on different planes. Growth from the openings is essentially determined by pattern confinement and minimization of the total surface energy, regardless of substrate orientations. A novel type-II WZ/ZB nanomembrane homojunction array is obtained by tailoring growth directions through alignment of the openings along certain crystallographic orientations. The understanding in this work lays the foundation for the design and fabrication of advanced III-V semiconductor devices based on complex geometrical nanostructures.

Orientation-Dependent Conversion of VLS-Grown Lead Iodide Nanowires into Organic-Inorganic Hybrid Perovskites

In this study, we demonstrate Sn-assisted vapor-liquid-solid (VLS) growth of lead iodide (PbI₂) nanowires with van der Waals layered crystal structure and subsequent vapor-phase conversion into methylammonium lead iodide (CH₃NH₃PbI₃) perovskites. Our systematic microscopic investigations confirmed that the VLS-grown PbI₂ nanowires display two major growth orientations of [0001] and [1¯21¯0], corresponding to the stacking configurations of PbI₂ layers to the nanowire axis (transverse for [0001] vs. parallel for [1¯21¯0]). The resulting difference in the sidewall morphologies was correlated with the perovskite conversion, where [0001] nanowires showed strong localized conversion at top and bottom, as opposed to [1¯21¯0] nanowires with an evenly distributed degree of conversion. An ab initio energy calculation suggests that CH₃NH₃I preferentially diffuses and intercalates into (112¯0) sidewall facets parallel to the [1¯21¯0] nanowire axis. Our results underscore the ability to control the crystal structures of van der Waals type PbI₂ in nanowire via the VLS technique, which is critical for the subsequent conversion process into perovskite nanostructures and corresponding properties.

Selective Area Epitaxy of GaAs/Ge/Si Nanomembranes: A Morphological Study

We demonstrate the feasibility of growing GaAs nanomembranes on a plastically-relaxed Ge layer deposited on Si (111) by exploiting selective area epitaxy in MBE. Our results are compared to the case of the GaAs homoepitaxy to highlight the criticalities arising by switching to heteroepitaxy. We found that the nanomembranes evolution strongly depends on the chosen growth parameters as well as mask pattern. The selectivity of III-V material with respect to the SiO2 mask can be obtained when the lifetime of Ga adatoms on SiO2 is reduced, so that the diffusion length of adsorbed Ga is high enough to drive the Ga adatoms towards the etched slits. The best condition for a heteroepitaxial selective area epitaxy is obtained using a growth rate equal to 0.3 ML/s of GaAs, with a As BEP pressure of about 2.5 × 10−6 torr and a temperature of 600 °C.

Template-assisted vapour-liquid-solid growth of InP nanowires on (001) InP and Si substrates

We report on the synthesis of vertical InP nanowire arrays on (001) InP and Si substrates using template-assisted vapour-liquid-solid growth. A thick silicon oxide layer was first deposited on the substrates. The samples were then patterned by electron beam lithography and deep dry etching through the oxide layer down to the substrate surface. Gold seed particles were subsequently deposited in the holes of the pattern by the use of pulse electrodeposition. The subsequent growth of nanowires by the vapour-liquid-solid method was guided towards the [001] direction by the patterned oxide template, and displayed a high growth yield with respect to the array of holes in the template. In order to confirm the versatility and robustness of the process, we have also demonstrated guided growth of InP nanowire p-n junctions and InP/InAs/InP nanowire heterostructures on (001) InP substrates. Our results show a promising route to monolithically integrate III-V nanowire heterostructure devices with commercially viable (001) silicon platforms.

GaAs nanoscale membranes: prospects for seamless integration of III-Vs on silicon

The growth of compound semiconductors on silicon has been widely sought after for decades, but reliable methods for defect-free combination of these materials have remained elusive. Recently, interconnected GaAs nanoscale membranes have been used as templates for the scalable integration of nanowire networks on III-V substrates. Here, we demonstrate how GaAs nanoscale membranes can be seamlessly integrated on silicon by controlling the density of nuclei in the initial stages of growth. We also correlate the absence or presence of defects with the existence of a single or multiple nucleation regime for the single membranes. Certain defects exhibit well-differentiated spectroscopic features that we identify with cathodoluminescence and micro-photoluminescence techniques. Overall, this work presents a new approach for the seamless integration of compound semiconductors on silicon.

Corner and side localization of electrons in irregular hexagonal semiconductor shells

We discuss the low energy electronic states in hexagonal rings. These states correspond to the transverse modes in core-shell nanowires built of III-V semiconductors which typically have a hexagonal cross section. In the case of symmetric structures the 12 lowest states (including the spin) are localized in the corners, while the next following 12 states are localized mostly on the sides. Depending on the material parameters, in particular the effective mass, the ring diameter and width, the corner and side states may be separated by a considerable energy gap, ranging from few to tens of meV. In a realistic fabrication process geometric asymmetries are unavoidable, and therefore the particles are not symmetrically distributed between all corner and side areas. Possibly, even small deformations may shift the localization of the ground state to one of the sides. The transverse states or the transitions between them may be important in transport or optical experiments. Still, up to date, there are only very few experimental investigations of the localization-dependent properties of core-shell nanowires.

Regaining a Spatial Dimension: Mechanically Transferrable Two-Dimensional InAs Nanofins Grown by Selective Area Epitaxy

We report a method for growing rectangular InAs nanofins with deterministic length, width, and height by dielectric-templated selective-area epitaxy. These freestanding nanofins can be transferred to lay flat on a separate substrate for device fabrication. A key goal was to regain a spatial dimension for device design compared to nanowires, while retaining the benefits of bottom-up epitaxial growth. The transferred nanofins were made into devices featuring multiple contacts for Hall effect and four-terminal resistance studies, as well as a global back-gate and nanoscale local top-gates for density control. Hall studies give a 3D electron density 2.5-5 × 10¹⁷ cm^-3, corresponding to an approximate surface accumulation layer density 3-6 × 10¹² cm^-2 that agrees well with previous studies of InAs nanowires. We obtain Hall mobilities as high as 1200 cm²/(V s), field-effect mobilities as high as 4400 cm²/(V s), and clear quantum interference structure at temperatures as high as 20 K. Our devices show excellent prospects for fabrication into more complicated devices featuring multiple ohmic contacts, local gates, and possibly other functional elements, for example, patterned superconductor contacts, that may make them attractive options for future quantum information applications.

Shape Engineering of InP Nanostructures by Selective Area Epitaxy

Greater demand for III-V nanostructures with more sophisticated geometries other than nanowires is expected because of the recent intensive investigation of nanowire networks that show great potential in all-optical logic gates, nanoelectronics, and quantum computing. Here, we demonstrate highly uniform arrays of InP nanostructures with tunable shapes, such as membrane-, prism-, and ring-like shapes, which can be simultaneously grown by selective area epitaxy. Our in-depth investigation of shape evolution confirms that the shape is essentially determined by pattern confinement and the minimization of total surface energy. After growth optimization, all of the different InP nanostructures grown under the same growth conditions show perfect wurtzite structure regardless of the geometry and strong and homogeneous photon emission. This work expands the research field in terms of producing nanostructures with the desired shapes beyond the limits of nanowires to satisfy various requirements for nanoelectronics, optoelectronics, and quantum device applications.

The Role of Polarity in Nonplanar Semiconductor Nanostructures

The lack of mirror symmetry in binary semiconductor compounds turns them into polar materials, where two opposite orientations of the same crystallographic direction are possible. Interestingly, their physical properties (e.g., electronic or photonic) and morphological features (e.g., shape, growth direction, and so forth) also strongly depend on the polarity. It has been observed that nanoscale materials tend to grow with a specific polarity, which can eventually be reversed for very specific growth conditions. In addition, polar-directed growth affects the defect density and topology and might induce eventually the formation of undesirable polarity inversion domains in the nanostructure, which in turn will affect the photonic and electronic final device performance. Here, we present a review on the polarity-driven growth mechanism at the nanoscale, combining our latest investigation with an overview of the available literature highlighting suitable future possibilities of polarity engineering of semiconductor nanostructures. The present study has been extended over a wide range of semiconductor compounds, covering the most commonly synthesized III-V (GaN, GaP, GaAs, GaSb, InN, InP, InAs, InSb) and II-VI (ZnO, ZnTe, CdS, CdSe, CdTe) nanowires and other free-standing nanostructures (tripods, tetrapods, belts, and membranes). This systematic study allowed us to explore the parameters that may induce polarity-dependent and polarity-driven growth mechanisms, as well as the polarity-related consequences on the physical properties of the nanostructures.