Experimental observation of negative capacitance in ferroelectrics at room temperature

Isomeric polythiophene: a promising material for low voltage electronic devices

In this investigation, we present empirical observations detailing the manifestation of substantial negative capacitance (NC), reaching up to -1 F, within iodine-doped isomeric polythiophene (IPTh-I2). NC observed in our case is not transient but stable enough to be measured for as long as the optimum concentration of the iodine dopant is available. In contrast, undoped isomeric polythiophene (IPTh) manifests a modest positive capacitance ranging from 30 to 60 μF. The concatenation of IPTh-I2 and IPTh in the series results in an augmentation of the total capacitance of the system (∼170 μF), exemplifying a characteristic feature of NC. Conversely, a bilayer configuration consisting of IPTh:IPTh exhibits a reduction in total capacitance by 38%. A notable amplification in the dielectric constant, escalating from 30 in IPTh to approximately 2000 in IPTh-I2, signifies extensive conformational and structural alterations arising from interactions between the doped polymer chain and various iodide species, attributing to the emergence of NC. Furthermore, we document a single-sided p-n junction diode with a low knee voltage (below 0.5 V) as a model device, illustrating the potential of IPTh as a promising material for the design and development of negative capacitance-based field-effect transistors. This research offers avenues for the scientific community to conceive low knee voltage-operating diodes, transistors, supercapacitors, and various other electronic devices based on all-organic semiconductors.

Ultralow Subthreshold Swing of a MOSFET Caused by Ferroelectric Polarization Reversal of Hf0.5Zr0.5O2 Thin Films

The emergence of complementary metal-oxide semiconductor (CMOS)-compatible HfO2-based ferroelectric materials provides a promising way to achieve ferroelectric field-effect transistors (FeFETs) with a steep subthreshold swing (SS) reduced to below the Boltzmann thermodynamics limit (∼60 mV/dec at room temperature), which has important implications for lowering power consumption. In this work, a metal-oxide-semiconductor field-effect transistor (MOSFET) is connected with Hf0.5Zr0.5O2 (HZO)-based ferroelectric capacitors with different capacitances. By adjusting the capacitance of ferroelectric capacitors, an ultralow SS of ∼0.34 mV/dec in HfO2-based FeFETs can be achieved. More interestingly, by designing the sweeping voltage sequences, the SS can be adjusted to be 0 mV/dec with the drain current ranging over six orders of magnitude, and the threshold voltage for turning on the MOSFET can be further reduced. The manipulated SS could be attributed to the evolution of ferroelectric switching. Our work contributes to understanding the origin of ultralow SS in ferroelectric MOSFETs and the realization of low-power devices.

Steep-Slope Transistor with an Imprinted Antiferroelectric Film

The effect of negative capacitance (NC), which can internally boost the voltage applied to a transistor, has been considered to overcome the fundamental Boltzmann limit of a transistor. To stabilize the NC effect, the dielectric (DE) must be integrated into a heterostructure with a ferroelectric (FE) film. However, in a multidomain hafnia, the charge boosting effect is reduced owing to a lowering of the depolarization field originating from the stray field at each domain, and simultaneously, the operating voltage increases owing to the voltage division at the DE. Here, we demonstrate core approaches to the gate stack of energy-efficient device technology using a transient NC. Electrical measurements of the transistor with imprinted antiferroelectric and high C_DE/C_FE structures exhibit low subthreshold slopes below 20 mV/dec, a low voltage operation of 0.5 V, a fast operation of 20 ns, hysteresis-free I_d-V_g, and high endurance characteristics of 10¹² cycles. We expect that this will lead to the rapid implementation of the NC effect in high-speed switching device applications with significantly improved energy efficiency.

Ultrathin ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage¹. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO₂ (ref. ²), which remains the material of choice to date. Here we report HfO₂-ZrO₂ superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO₂ thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO₂-based high-dielectric-constant gate stacks without scavenging the interfacial SiO₂, which has adverse effects on the electron transport and gate leakage current³. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO₂-ZrO₂ multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO₂-based high-dielectric-constant materials.

Macroscopic and microscopic picture of negative capacitance operation in ferroelectric capacitors

The negative capacitance (NC) operation of ferroelectric materials has been originally proposed based on a homogeneous Landau theory, leading to a simple NC stabilization condition expressed in terms of macroscopic quantities. A multi-domain theory, however, has pointed out the importance of microscopic parameters, such as the domain wall energy coupling constant, and it helped explain the somewhat contradicting experiments for ferroelectric capacitors with or without a metal interlayer. In this work we use comprehensive numerical simulations and simplified equations to correlate the macroscopic features of the NC operation to the underlying microscopic picture. We show that, while the domain wall coupling constant plays a critical role in a quasi static operation, the transient NC operation is less sensitive to this parameter. In particular, ferroelectric capacitors with a very small coupling constant can still display a robust transient NC behavior, closely tracking the 'S'-shaped polarization versus field curve and with negligible hysteresis. Our results have been developed in the framework of a systematic comparison between simulations and experiments, and they provide both a better understanding of the NC operation and a sound basis for the design of future NC based devices.

Energy-efficient transistors: suppressing the subthreshold swing below the physical limit

With the miniaturization of silicon-based electronic components, power consumption is becoming a fundamental issue for micro-nano electronic circuits. The main reason for this is that the scaling of the supply voltage in the ultra-large-scale integrated circuit cannot keep up with the shrinking of the characteristic size of conventional transistors due to the physical limit termed "Boltzmann Tyranny", in which a gate voltage of at least 60 mV is required to modulate the drain current by one order of magnitude. Accordingly, to solve this problem, several new transistor architectures have been designed to reduce the subthreshold swing (SS) to lower than the fundamental limitation, thus lowering the supply voltage and reducing the power consumption. In this review, we first analytically formulate the SS, summarize the methods for reducing the SS, and propose four new transistor concepts, including tunnelling field-effect transistor, negative capacitance field-effect transistor, impact ionization field-effect transistor, and cold source field-effect transistor. Then, we review their physical mechanisms and optimization methods and consider the potential and drawbacks of these four new transistors. Finally, we discuss the challenges encountered in the investigation of these steep-slope transistors and present the future outlook.

High-current MoS2 transistors with non-planar gate configuration

The ever-decreasing size of transistors requires effectively electrostatic control over ultra-thin semiconductor body. Rational design of the gate configuration can fully persevere the intrinsic property of two-dimensional (2D) semiconductors. Here we design and demonstrate a 2D MoS₂ transistor with omega-shaped gate, in which the local gate coupling is enhanced by the non-planar geometry. The omega-shaped non-planar transistors exhibit a high current of 0.89 A/μm and transconductance of 32.7 μS/μm. The high performance and desirable current saturation promise the construction of robust logic gate. The inverters show a voltage gain of 26.6 and an ideal total margin nearly 89%. We also assemble NOT-AND (NAND) gate on an individual MoS₂ flake, and the constructed NAND gate demonstrates the universal functionality of the transistors as well. This work provides an alternative strategy to fully take the advantages of 2D materials for high-performance field-effect transistors.

Local negative permittivity and topological phase transition in polar skyrmions

Topological solitons such as magnetic skyrmions have drawn attention as stable quasi-particle-like objects. The recent discovery of polar vortices and skyrmions in ferroelectric oxide superlattices has opened up new vistas to explore topology, emergent phenomena and approaches for manipulating such features with electric fields. Using macroscopic dielectric measurements, coupled with direct scanning convergent beam electron diffraction imaging on the atomic scale, theoretical phase-field simulations and second-principles calculations, we demonstrate that polar skyrmions in (PbTiO₃)_n/(SrTiO₃)_n superlattices are distinguished by a sheath of negative permittivity at the periphery of each skyrmion. This enhances the effective dielectric permittivity compared with the individual SrTiO₃ and PbTiO₃ layers. Moreover, the response of these topologically protected structures to electric field and temperature shows a reversible phase transition from the skyrmion state to a trivial uniform ferroelectric state, accompanied by large tunability of the dielectric permittivity. Pulsed switching measurements show a time-dependent evolution and recovery of the skyrmion state (and macroscopic dielectric response). The interrelationship between topological and dielectric properties presents an opportunity to simultaneously manipulate both by a single, and easily controlled, stimulus, the applied electric field.

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO₂ as ferroelectric materials.

Stepwise internal potential jumps caused by multiple-domain polarization flips in metal/ferroelectric/metal/paraelectric/metal stack

Negative capacitance (NC) effects in ferroelectric/paraelectric (FE/PE) stacks have been recently discussed intensively in terms of the steep subthreshold swing (SS) in field-effect transistors (FETs). It is, however, still disputable to stabilize quasi-static-NC effects. In this work, stepwise internal potential jumps in a metal/FE/metal/PE/metal system observed near the coercive voltage of the FE layer are reported through carefully designed DC measurements. The relationship of the internal potential jumps with the steep SS in FETs is also experimentally confirmed by connecting a FE capacitor to a simple metal-oxide-semiconductor FET. On the basis of the experimental results, the observed internal potential jumps are analytically modelled from the viewpoint of bound charge emission associated with each domain flip in a multiple-domain FE layer in a FE/PE stack. This view is different from the original NC concept and should be employed for characterizing FE/PE gate stack FETs.

Negative capacitance (NC) effects that could allow steep subthreshold swing (SS) in field-effect transistors (FETs) are still controversially discussed. Here the authors propose a model distinct from the NC concept, taking into account domain flips in multiple-domain ferroelectric/paraelectric gate stack FETs.

Switching On/Off Negative Capacitance in Ultrathin Ferroelectric/Dielectric Capacitors

Ferroelectric (FE) and dielectric (DE) insulator bilayer stacks provide a promising gate for low-power microelectronic devices. To fully realize the FE polarization switching, the DE layer must be ultrathin in the FE/DE bilayer stack. Motivated by this, this work presents the first successful fabrication and characterization of Fe/FeO_x/Al₂O₃/Fe FE/DE bilayer capacitors using in vacuo atomic layer deposition (ALD) with a total FE/DE stack thickness <3-4 nm. A key tuning parameter in generating the FE/DE bilayer capacitors is the thickness of an Al wetting layer between the bottom Fe electrode and the ALD-Al₂O₃ DE layer. At a large thickness in exceeding 1.0 nm, high-quality conventional DE capacitors of 2.2 nm thick ALD-Al₂O₃ were obtained with dielectric constant (ε_r) ∼8.0 that is close to ε_r ∼ 9.2 for the Al₂O₃ bulk single crystal with an effective oxide thickness of 1.0 nm. By reducing the Al wetting layer thickness to below 1.0 nm, a thin ferroelectric FeO_x interfacial layer of a thickness of 1-2 nm forms, enabling the achievement of a FeO_x/Al₂O₃ FE/DE bilayer capacitor with static negative capacitance. Since all ferroelectric materials are piezoelectric, we show that a dynamic switching on/off of the negative capacitance can be achieved under the application of an external force on the ultrathin FE/DE capacitors through manipulation of the electric dipoles. This result not only provides a viable approach for generating ultrathin FE/DE bilayer capacitors but also offers a promising solution to low-power consumption microelectronics.

Negative capacitance switching in size-modulated Fe3O4 nanoparticles with spontaneous non-stoichiometry: confronting its generalized origin in non-ferroelectric materials

Persistent low-frequency negative capacitance (NC) dispersion has been detected in half-metallic polycrystalline magnetite (Fe3O4) nanoparticles with varying sizes from 13 to 236 nm under the application of moderate dc bias. Using the Havriliak-Negami model, 3D Cole-Cole plots were employed to recapitulate the relaxation times (τ) of the associated oscillating dipoles, related shape parameters (α, β) and resistivity for the nanoparticles with different sizes. The universal Debye relaxation (UDR) theory requires a modification to address the shifted quasi-static NC-dispersion plane in materials showing both +ve and -ve capacitances about a transition/switching frequency (f0). A consistent blue-shift in 'f0' is observed with increasing external dc field and decreasing particle size. Based on this experimental data, a generalized dispersion scheme is proposed to fit the entire positive and negative capacitance regime, including the diverging transition point. In addition, a comprehensive model is discussed using phasor diagrams to differentiate the underlying mechanisms of the continuous transition from -ve to +ve capacitance involving localized charge recombination or time-dependent injection/displacement currents, which has been adequately explored in the scientific literature, and the newly proposed 'capacitive switching' phenomenon. An inherent non-stoichiometry due to iron vacancies [Fe3(1-δ)O4], duly validated from first principles calculations, builds up p-type nature, which consequently promotes more covalent and heavier dipoles and slows the dipolar relaxations; this is incommensurate with Maxwell-Wagner interfacial polarization (MWIP) dynamics. This combinatorial effect is likely responsible for the sluggish response of the associated dipoles and the stabilization of NC.

Comprehensive study of high pressure annealing on the ferroelectric properties of Hf0.5Zr0.5O2 thin films

Thin films of ferroelectric materials are potential candidates to be implemented in the unfolding of a new paradigm in high-density memory devices. As the thickness of these films reaches the sub-10 nm level, the interface properties between the electrode and ferroelectric material undergo significant changes that play a crucial role in governing the ferroelectric behavior. The present state-of-the-art approach presents a detailed investigation of different high pressure annealing (HPA) conditions through simulation studies. The simulation studies were performed using Landau-Khalatnikov equations, with Landau's parameters calculated using the least regression method as described in the Method S1. The extracted coefficients were used to determine various relationships (free energy, ferroelectric potential and negative capacitance) with which to observe the impact of HPA on the negative capacitance (NC) effect on account of the majority ferroelectric phase. To verify the simulation results, pulse transient switching measurements were conducted using Pt/Ti/TiN/Hf_0.5Zr_0.5O₂/TiN-based metal-ferroelectric-metal (MFM) devices to study the coercive field, interfacial capacitance and load resistance behavior. The results suggest that the non-ferroelectric portion (t-phase) coexists with the ferroelectric (o-phase) within the thin layer of the MFM capacitor adjacent to TiN electrode, which undergoes a phase transformation from the t-phase to the o-phase when exposed to different HPA conditions as well as electric field cycling during PS measurements. The simulation and experimental results confirm that the 550 °C at 50 atm N₂ environment provides the best possibility of achieving the highest ferroelectric characteristics with the lowest proportion of the non-ferroelectric phase and thus the maximum NC effect as well.

Why Do Ferroelectrics Exhibit Negative Capacitance?

The Landau theory of phase transitions predicts the presence of a negative capacitance in ferroelectric materials based on a mean-field approach. While recent experimental results confirm this prediction, the microscopic origin of negative capacitance in ferroelectrics is often debated. This study provides a simple, physical explanation of the negative capacitance phenomenon—i.e., ‘S’-shaped polarization vs. electric field curve—without having to invoke the Landau phenomenology. The discussion is inspired by pedagogical models of ferroelectricity as often presented in classic text-books such as the Feynman lectures on Physics and the Introduction of Solid State Physics by Charles Kittel, which are routinely used to describe the quintessential ferroelectric phenomena such as the Curie-Weiss law and the emergence of spontaneous polarization below the Curie temperature. The model presented herein is overly simplified and ignores many of the complex interactions in real ferroelectrics; however, this model reveals an important insight: The polarization catastrophe phenomenon that is required to describe the onset of ferroelectricity naturally leads to the thermodynamic instability that is negative capacitance. Considering the interaction of electric dipoles and saturation of the dipole moments at large local electric fields we derive the full ‘S’-curve relating the ferroelectric polarization and the electric field, in qualitative agreement with Landau theory.

Modeling of Negative Capacitance in Ferroelectric Thin Films

The negative capacitance (NC) effect in ferroelectric thin films has attracted a great deal of attention from the material and semiconductor device communities because it could be a possible solution to the impending problems related to field-effect transistor power consumption and dynamic random-access memory charge loss. A short discussion on the fundamental premise of the NC effect is presented. A phase-field model based on the time-dependent Ginzburg-Landau (TDGL) formalism in conjunction with the Chensky-Tarasenko (C-T) formalism for multidomain configuration is then developed to reveal the subtle correlation between the domain wall motion and NC effect for different thicknesses of ferroelectric and dielectric films. When a ferroelectric film becomes thin enough, a stripe domain structure can be achieved through competition between the electrostatic energy and domain wall energy. This stripe domain structure is quite resilient to transition to a homogeneous polarization state, making it very useful for (quasi-)static NC operation. Finally, the physical implications of the numerical results are explored with analytical modeling. It is identified that the domain wall motion in the stripe domain structure remains dominated by the external field, even when the entire film is in the (quasi-)static NC state.

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Negative Capacitance (NC) in ferroelectric materials is proposed in order to address this physical limitation of CMOS technology. A polarization destabilization in ferroelectrics causes an effective negative permittivity, resulting in a differential voltage amplification and a reduced subthreshold swing when integrated into the gate stack of a transistor. The novelty and universality of this approach relate to the fact that the gate stack is not anymore a passive part of the transistor and contributes to signal amplification. In this paper, we experimentally validate NC as a universal performance booster: (i) for complementary MOSFETs, of both n- and p-type in an advanced CMOS technology node, and, (ii) for both digital and analog significant enhancements of key figures of merit for information processing (subthreshold swing, overdrive, and current efficiency factor). Accordingly, a sub-thermal swing down to 10 mV/decade together with an enhanced current efficiency factor up to 10⁵ V⁻¹ is obtained in both n- and p-type MOSFETs at room temperature by exploiting a PZT capacitor as the NC booster. As a result of the subthreshold swing reduction and overdrive improvement observed by NC, the required supply voltage to provide the same on-current is reduced by approximately 50%.

Unveiling the double-well energy landscape in a ferroelectric layer

The properties of ferroelectric materials, which were discovered almost a century ago¹, have led to a huge range of applications, such as digital information storage², pyroelectric energy conversion³ and neuromorphic computing^4,5. Recently, it was shown that ferroelectrics can have negative capacitance^6-11, which could improve the energy efficiency of conventional electronics beyond fundamental limits^12-14. In Landau-Ginzburg-Devonshire theory^15-17, this negative capacitance is directly related to the double-well shape of the ferroelectric polarization-energy landscape, which was thought for more than 70 years to be inaccessible to experiments¹⁸. Here we report electrical measurements of the intrinsic double-well energy landscape in a thin layer of ferroelectric Hf_0.5Zr_0.5O₂. To achieve this, we integrated the ferroelectric into a heterostructure capacitor with a second dielectric layer to prevent immediate screening of polarization charges during switching. These results show that negative capacitance has its origin in the energy barrier in a double-well landscape. Furthermore, we demonstrate that ferroelectric negative capacitance can be fast and hysteresis-free, which is important for prospective applications¹⁹. In addition, the Hf_0.5Zr_0.5O₂ used in this work is currently the most industry-relevant ferroelectric material, because both HfO₂ and ZrO₂ thin films are already used in everyday electronics²⁰. This could lead to fast adoption of negative capacitance effects in future products with markedly improved energy efficiency.

Sub-kT/q switching in In2O3 nanowire negative capacitance field-effect transistors

Limited by the Boltzmann distribution of electrons, the sub-threshold swing (SS) of conventional MOSFETs cannot be less than 60 mV dec-1. This limitation hinders the reduction of power dissipation of the devices. Herein, we present high-performance In2O3 nanowire (NW) negative capacitance field-effect transistors (NC-FETs) by introducing a ferroelectric P(VDF-TrFE) layer in a gate dielectric stack. The fabricated devices exhibit excellent gate modulation with a high saturation current density of 550 μA μm-1 and an outstanding SS value less than 60 mV dec-1 for over 4 decades of channel current. The assembled inverter circuit can demonstrate an impressive voltage gain of 25 and a cut-off frequency of over 10 MHz. By utilizing the self-aligned fabrication scheme, the device can be ultimately scaled down to below 100 nm channel length. The devices with 200 nm channel length exhibit the best performances, in which a high on/off current ratio of >107, a large output current density of 960 μA μm-1 and a small SS value of 42 mV dec-1 are obtained at the same time. All these would not only evidently demonstrate the potency of NW NC-FETs to break through the Boltzmann limit in nanoelectronics, but also open up a new avenue to low-power transistors for portable products.

MoS2 Negative-Capacitance Field-Effect Transistors with Subthreshold Swing below the Physics Limit

The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec^-1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS₂ negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec^-1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10⁶ with channel length less than 100 nm. Furthermore, the inserted HfO₂ layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS₂ NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products.

On the stabilization of ferroelectric negative capacitance in nanoscale devices

Recently, the proposal to use voltage amplification from ferroelectric negative capacitance (NC) to reduce the power dissipation in nanoelectronic devices has attracted significant attention. Homogeneous Landau theory predicts, that by connecting a ferroelectric in series with a dielectric capacitor, a hysteresis-free NC state can be stabilized in the ferroelectric below a critical film thickness. However, there is a strong discrepancy between experimental results and the current theory. Here, we present a comprehensive revision of the theory of NC stabilization with respect to scaling of material and device dimensions based on multi-domain Ginzburg-Landau theory. It is shown that the use of a metal layer in between the ferroelectric and the dielectric will inherently destabilize NC due to domain formation. However, even without this metal layer, domain formation can reduce the critical ferroelectric thickness considerably, limiting not only the range of NC stabilization, but also the maximum amplification attainable. To overcome these obstacles, the downscaling of lateral device dimensions is proposed as a way to prevent domain formation and to enhance the voltage amplification due to NC. These insights will be crucial for future NC device design and scaling towards nanoscale dimensions.

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

This work experimentally demonstrates that the negative capacitance effect can be used to significantly improve the key figures of merit of tunnel field effect transistor (FET) switches. In the proposed approach, a matching condition is fulfilled between a trained-polycrystalline PZT capacitor and the tunnel FET (TFET) gate capacitance fabricated on a strained silicon-nanowire technology. We report a non-hysteretic switch configuration by combining a homojunction TFET and a negative capacitance effect booster, suitable for logic applications, for which the on-current is increased by a factor of 100, the transconductance by 2 orders of magnitude, and the low swing region is extended. The operation of a hysteretic negative capacitance TFET, when the matching condition for the negative capacitance is fulfilled only in a limited region of operation, is also reported and discussed. In this late case, a limited improvement in the device performance is observed. Overall, the paper demonstrates the main beneficial effects of negative capacitance on TFETs are the overdrive and transconductance amplification, which exactly address the most limiting performances of current TFETs.

Steep switching devices for low power applications: negative differential capacitance/resistance field effect transistors

Simply including either single ferroelectric oxide layer or threshold selector, we can make conventional field effect transistor to have super steep switching characteristic, i.e., sub-60-mV/decade of subthreshold slope. One of the representative is negative capacitance FET (NCFET), in which a ferroelectric layer is added within its gate stack. The other is phase FET (i.e., negative resistance FET), in which a threshold selector is added to an electrode (e.g., source or drain) of conventional field effect transistor. Although the concept of the aforementioned two devices was presented more or less recently, numerous studies have been published. In this review paper, by reviewing the published studies over the last decade, we shall de-brief and discuss the history and the future perspectives of NCFET/phase FET, respectively. The background, experimental investigation, and future direction for developing the aforementioned two representative steep switching devices (i.e., NCFET and phase FET/negative resistance FET) are to be discussed in detail.

An Unusual Mechanism for Negative Differential Resistance in Ferroelectric Nanocapacitors: Polarization Switching-Induced Charge Injection Followed by Charge Trapping

Negative differential resistance (NDR) has been extensively investigated for its wide device applications. However, a major barrier ahead is the low reliability. To address the reliability issues, we consider ferroelectrics and propose an alternative mechanism for realizing the NDR with deterministic current peak positions, in which the NDR results from the polarization switching-induced charge injection and subsequent charge trapping at the metal/ferroelectric interface. In this work, ferroelectric Au/BiFe_0.6Ga_0.4O₃ (BFGO)/Ca_0.96Ce_0.04MnO₃ (CCMO) nanocapacitors are prepared, and their ferroelectricity and NDR behaviors are studied concurrently. It is observed that the NDR current peaks are located at the vicinity of coercive voltages (V_c) of the ferroelectric nanocapacitors, thus evidencing the proposed mechanism. In addition, the NDR effect is reproducible and robust with good endurance and long retention time. This study therefore demonstrates a ferroelectric-based NDR device, which may facilitate the development of highly reliable NDR devices.

Sustained Sub-60 mV/decade Switching via the Negative Capacitance Effect in MoS2 Transistors

It has been shown that a ferroelectric material integrated into the gate stack of a transistor can create an effective negative capacitance (NC) that allows the device to overcome "Boltzmann tyranny". While this switching below the thermal limit has been observed with Si-based NC field-effect transistors (NC-FETs), the adaptation to 2D materials would enable a device that is scalable in operating voltage as well as size. In this work, we demonstrate sustained sub-60 mV/dec switching, with a minimum subthreshold swing (SS) of 6.07 mV/dec (average of 8.03 mV/dec over 4 orders of magnitude in drain current), by incorporating hafnium zirconium oxide (HfZrO₂ or HZO) ferroelectric into the gate stack of a MoS₂ 2D-FET. By first fabricating and characterizing metal-ferroelectric-metal capacitors, the MoS₂ is able to be transferred directly on top and characterized with both a standard and a negative capacitance gate stack. The 2D NC-FET exhibited marked enhancement in low-voltage switching behavior compared to the 2D-FET on the same MoS₂ channel, reducing the SS by 2 orders of magnitude. A maximum internal voltage gain of ∼28× was realized with ∼12 nm thick HZO. Several unique dependencies were observed, including threshold voltage (V_th) shifts in the 2D NC-FET (compared to the 2D-FET) that correlate with source/drain overlap capacitance and changes in HZO (ferroelectric) and HfO₂ (dielectric) thicknesses. Remarkable sub-60 mV/dec switching was obtained from 2D NC-FETs of various sizes and gate stack thicknesses, demonstrating great potential for enabling size- and voltage-scalable transistors.

Negative Capacitance in BaTiO3/BiFeO3 Bilayer Capacitors

Negative capacitances provide an approach to reduce heat generations in field-effect transistors during the switch processes, which contributes to further miniaturization of the conventional integrated circuits. Although there are many studies about negative capacitances using ferroelectric materials, the direct observation of stable ferroelectric negative capacitances has rarely been reported. Here, we put forward a dc bias assistant model in bilayer capacitors, where one ferroelectric layer with large dielectric constant and the other ferroelectric layer with small dielectric constant are needed. Negative capacitances can be obtained when external dc bias electric fields are larger than a critical value. Based on the model, BaTiO3/BiFeO3 bilayer capacitors are chosen as study objects, and negative capacitances are observed directly. Additionally, the upward self-polarization effect in the ferroelectric layer reduces the critical electric field, which may provide a method for realizing zero and/or small dc bias assistant negative capacitances.

Time-Dependent Negative Capacitance Effects in Al2O3/BaTiO3 Bilayers

The negative capacitance (NC) effects in ferroelectric materials have emerged as the possible solution to low-power transistor devices and high-charge-density capacitors. Although the steep switching characteristic (subthreshold swing < sub-60 mV/dec) has been demonstrated in various devices combining the conventional transistors with ferroelectric gates, the actual applications of the NC effects are still some way off owing to the inherent hysteresis problem. This work reinterpreted the hysteretic properties of the NC effects within the time domain and demonstrated that capacitance (charge) boosting could be achieved without the hysteresis from the Al2O3/BaTiO3 bilayer capacitors through short-pulse charging. This work revealed that the hysteresis phenomenon in NC devices originated from the dielectric leakage of the dielectric layer. The suppression of charge injection via the dielectric leakage, which usually takes time, inhibits complete ferroelectric polarization switching during a short pulse time. It was demonstrated that a nonhysteretic NC effect can be achieved only within certain limited time and voltage ranges, but that these are sufficient for critical device applications.

New modalities of strain-control of ferroelectric thin films

Ferroelectrics, with their spontaneous switchable electric polarization and strong coupling between their electrical, mechanical, thermal, and optical responses, provide functionalities crucial for a diverse range of applications. Over the past decade, there has been significant progress in epitaxial strain engineering of oxide ferroelectric thin films to control and enhance the nature of ferroelectric order, alter ferroelectric susceptibilities, and to create new modes of response which can be harnessed for various applications. This review aims to cover some of the most important discoveries in strain engineering over the past decade and highlight some of the new and emerging approaches for strain control of ferroelectrics. We discuss how these new approaches to strain engineering provide promising routes to control and decouple ferroelectric susceptibilities and create new modes of response not possible in the confines of conventional strain engineering. To conclude, we will provide an overview and prospectus of these new and interesting modalities of strain engineering helping to accelerate their widespread development and implementation in future functional devices.

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at -0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm(2)/Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature.

Alternative interpretations for decreasing voltage with increasing charge in ferroelectric capacitors

Recent claim on the direct observation of a negative capacitance (NC) effect from a single layer epitaxial Pb(Zr0.2,Ti0.8)O3 (PZT) thin film was carefully reexamined, and alternative interpretations that can explain the experimental results without invoking the NC effect are provided. Any actual ferroelectric capacitor has an interfacial layer, and experiment always measures the sum of voltages across the interface layer and the ferroelectric layer. The main observation of decreasing ferroelectric capacitor voltage (VF) for increasing ferroelectric capacitor charge (QF), claimed to be the direct evidence for the NC effect, could be alternatively interpreted by either the sudden increase in the positive capacitance of a ferroelectric capacitor or decrease in the voltage across the interfacial layer due to resistance degradation. The experimental time-transient VF and QF could be precisely simulated by these alternative models that fundamentally assumes the reverse domain nucleation and growth. Supplementary experiments using an epitaxial BaTiO3 film supported this claim. This, however, does not necessarily mean that the realization of the NC effect within the ferroelectric layer is impractical under appropriate conditions. Rather, the circuit suggested by Khan et al. may not be useful to observe the NC effect directly.

Emergence of Negative Capacitance in Multidomain Ferroelectric-Paraelectric Nanocapacitors at Finite Bias

The emergence of negative capacitance in an ultrathin ferroelectric/paraelectric bilayer capacitor under electrical bias is examined using first-principles simulation. An antiferroelectric-like behavior is predicted, and negative capacitance is shown to emerge when the monodomain state becomes stable after bias application. The polydomain-monodomain transition is also shown to be a source of capacitance enhancement.

Frustration of Negative Capacitance in Al2O3/BaTiO3 Bilayer Structure

Enhancement of capacitance by negative capacitance (NC) effect in a dielectric/ferroelectric (DE/FE) stacked film is gaining a greater interest. While the previous theory on NC effect was based on the Landau-Ginzburg-Devonshire theory, this work adopted a modified formalism to incorporate the depolarization effect to describe the energy of the general DE/FE system. The model predicted that the SrTiO3/BaTiO3 system will show a capacitance boost effect. It was also predicted that the 5 nm-thick Al2O3/150 nm-thick BaTiO3 system shows the capacitance boost effect with no FE-like hysteresis behavior, which was inconsistent with the experimental results; the amorphous-Al2O3/epitaxial-BaTiO3 system showed a typical FE-like hysteresis loop in the polarization - voltage test. This was due to the involvement of the trapped charges at the DE/FE interface, originating from the very high field across the thin Al2O3 layer when the BaTiO3 layer played a role as the NC layer. Therefore, the NC effect in the Al2O3/BaTiO3 system was frustrated by the involvement of reversible interface charge; the highly stored charge by the NC effect of the BaTiO3 during the charging period could not be retrieved during the discharging process because integral part of the polarization charge was retained within the system as a remanent polarization.

An improved model for the surface potential and drain current in negative capacitance field effect transistors

An improved model for the surface potential and drain current in negative capacitance ferroelectric field effect transistors (NC-FeFETs) was presented by introducing the doping concentration.

Evidence of Negative Capacitance in Piezoelectric ZnO Thin Films Sputtered on Interdigital Electrodes

The scaling paradigm known as Moore's Law, with the shrinking of transistors and their doubling on a chip every two years, is going to reach a painful end. Another less-known paradigm, the so-called Koomey's Law, stating that the computing efficiency doubles every 1.57 years, poses other important challenges, since the efficiency of rechargeable energy sources is substantially constant, and any other evolution is based on device architecture only. How can we still increase the computational power/reduce the power consumption of our electronic environments? A first answer to this question comes from the quest for new functionalities. Within this aim, negative capacitance (NC) is becoming one of the most intriguing and studied phenomena since it can be exploited for reducing the aforementioned limiting effects in the downscaling of electronic devices. Here we report the evidence of negative capacitance in 80 nm thick ZnO thin films sputtered on Au interdigital electrodes (IDEs). Highly (002)-oriented ZnO thin films, with a fine-grained surface nanostructure and the desired chemical composition, are deposited at room temperature on different IDEs structures. Direct-current electrical measurements highlighted the semiconducting nature of ZnO (current density in the order of 1 × 10(-3) A/cm(2)). When turned into the alternating current regime (from 20 Hz to 2 MHz) the presence of NC values is observed in the low-frequency range (20-120 Hz). The loss of metal/semiconductor interface charge states under forward bias conditions, together with the presence of oxygen vacancies and piezoelectric/electrostriction effects, is believed to be at the basis of the observed negative behavior, suggesting that ZnO thin-film-based field-effect transistors can be a powerful instrument to go beyond the Boltzmann limit and the downscaling of integrated circuit elements required for the fabrication of portable and miniaturized electronic devices, especially for electric household appliances working in the low 50 Hz utility frequency.

Negative Capacitance in Organic/Ferroelectric Capacitor to Implement Steep Switching MOS Devices

Because of the "Boltzmann tyranny" (i.e., the nonscalability of thermal voltage), a certain minimum gate voltage in metal-oxide-semiconductor (MOS) devices is required for a 10-fold increase in drain-to-source current. The subthreshold slope (SS) in MOS devices is, at best, 60 mV/decade at 300 K. Negative capacitance in organic/ferroelectric materials is proposed in order to address this physical limitation in MOS technology. Here, we experimentally demonstrate the steep switching behavior of a MOS device-that is, SS ∼ 18 mV/decade (much less than 60 mV/decade) at 300 K-by taking advantage of negative capacitance in a MOS gate stack. This negative capacitance, originating from the dynamics of the stored energy in a phase transition of a ferroelectric material, can achieve the step-up conversion of internal voltage (i.e., internal voltage amplification in a MOS device). With the aid of a series-connected negative capacitor as an assistive device, the surface potential in the MOS device becomes higher than the applied gate voltage, so that a SS of 18 mV/decade at 300 K is reliably observed.

A review of molecular beam epitaxy of ferroelectric BaTiO3 films on Si, Ge and GaAs substrates and their applications

SrTiO₃ epitaxial growth by molecular beam epitaxy (MBE) on silicon has opened up the route to the monolithic integration of various complex oxides on the complementary metal-oxide-semiconductor silicon platform. Among functional oxides, ferroelectric perovskite oxides offer promising perspectives to improve or add functionalities on-chip. We review the growth by MBE of the ferroelectric compound BaTiO₃ on silicon (Si), germanium (Ge) and gallium arsenide (GaAs) and we discuss the film properties in terms of crystalline structure, microstructure and ferroelectricity. Finally, we review the last developments in two areas of interest for the applications of BaTiO₃ films on silicon, namely integrated photonics, which benefits from the large Pockels effect of BaTiO₃, and low power logic devices, which may benefit from the negative capacitance of the ferroelectric.

Negative capacitance in a ferroelectric capacitor

The Boltzmann distribution of electrons poses a fundamental barrier to lowering energy dissipation in conventional electronics, often termed as Boltzmann Tyranny. Negative capacitance in ferroelectric materials, which stems from the stored energy of a phase transition, could provide a solution, but a direct measurement of negative capacitance has so far been elusive. Here, we report the observation of negative capacitance in a thin, epitaxial ferroelectric film. When a voltage pulse is applied, the voltage across the ferroelectric capacitor is found to be decreasing with time--in exactly the opposite direction to which voltage for a regular capacitor should change. Analysis of this 'inductance'-like behaviour from a capacitor presents an unprecedented insight into the intrinsic energy profile of the ferroelectric material and could pave the way for completely new applications.

Room-temperature negative capacitance in a ferroelectric-dielectric superlattice heterostructure

We demonstrate room-temperature negative capacitance in a ferroelectric-dielectric superlattice heterostructure. In epitaxially grown superlattice of ferroelectric BSTO (Ba0.8Sr0.2TiO3) and dielectric LAO (LaAlO3), capacitance was found to be larger compared to the constituent LAO (dielectric) capacitance. This enhancement of capacitance in a series combination of two capacitors indicates that the ferroelectric was stabilized in a state of negative capacitance. Negative capacitance was observed for superlattices grown on three different substrates (SrTiO3 (001), DyScO3 (110), and GdScO3 (110)) covering a large range of substrate strain. This demonstrates the robustness of the effect as well as potential for controlling the negative capacitance effect using epitaxial strain. Room-temperature demonstration of negative capacitance is an important step toward lowering the subthreshold swing in a transistor below the intrinsic thermodynamic limit of 60 mV/decade and thereby improving energy efficiency.