Double-Gate MoS2 Field-Effect Transistors with Full-Range Tunable Threshold Voltage for Multifunctional Logic Circuits

Van der Waals Inverted-Floating-Gate Transistors for Artificial Intelligence Electronics

An inverted floating gate device architecture is introduced, demonstrated with all-van-der-Waals technology, targeting both logic and neuromorphic circuits. Integrating a top polymorphic multilayer graphene floating gate improves the electrostatic coupling to the ReS2 semiconductor channel by facilitating efficient dynamic conductance tuning and enabling dual-mode reconfigurable logic and memory operations. The non-volatile capability is used to implement compact logic gates for in-memory computing. The device is also shown to emulate synaptic plasticity, with an accuracy of 92% demonstrated in simple artificial neural network simulations. Moreover, spiking neuron circuits for neural networks through a five-transistor design makes it a versatile building block for artificial intelligence electronics. These findings demonstrate the potential of hybrid integration of van der Waals materials to address the limitations of traditional semiconductor technologies and become key to developments of next-generation electronics.

Light-induced tunable threshold voltage and synaptic behavior of a solution-processed indium oxide thin film transistor for logic computing and image denoising

Oxygen vacancies (VO) play a crucial role in promising amorphous metal oxide films for next-generation logic and synaptic computing. Here, a simple and reversible annealing-illumination method is introduced to control the concentration of VO in solution-processed amorphous indium oxide thin-film transistors (TFTs), resulting in the precise regulation of the threshold voltage (VTH) in a large range from 1.6 V to -21.7 V. Meanwhile, clear photo-synaptic behaviors are observed. These impressive behaviors result from the VO-related carrier trapping and detrapping processes. With the precise regulation of VTH by illumination, the TFTs are constructed as inverters, displaying tunable voltage gains from 5.7 to 10.6. Owing to the excellent photo-synaptic behavior, the TFTs are employed to demonstrate the optoelectronic logic functions of "OR", "AND", "NOR", and "NAND". Moreover, a 5 × 5 TFTs array is employed to demonstrate the real-time image preprocessing and image denoising functions, displaying an impressive accuracy of 96%. Furthermore, the improvement of the recognition accuracy will increase to a maximum value of 88%. This work shows the potential of amorphous indium oxide TFTs in future multifunctional logic circuits and efficient, all-optical neuromorphic vision systems.

2D edge-seeded heteroepitaxy of ultrathin high-κ dielectric CaNb2O6 for 2D field-effect transistors

The experimental realization of single-crystalline high-κ dielectrics beyond two-dimensional (2D) layered materials is highly desirable for nanoscale field-effect transistors (FETs). However, the scalable synthesis of 2D nonlayered high-κ insulators is currently limited by uncontrolled isotropic three-dimensional growth, hampering the achievement of simultaneous high dielectric constants and low trap densities for small film thicknesses. Herein, we show a 2D edge-seeded heteroepitaxial strategy to synthesize ultrathin nonlayered 2D CaNb2O6 nanosheets by chemical vapor deposition, exhibiting high-crystalline quality, thickness-independent dielectric constant (~ 16) and breakdown field strength up to ~ 12 MV cm-1. The MoS2/CaNb2O6 FETs exhibit an on/off ratio of over ~ 107, a subthreshold swing down to 61 mV/dec and a negligible hysteresis. This work suggests a universal 2D edge-seeded heteroepitaxy and slow kinetic strategy for the scalable growth of 2D nonlayered dielectric and demonstrates 2D CaNb2O6 nanosheets as promising dielectrics for facilitating 2D electronic applications.

Low-Power and High-Gain Organic Transistors Achieved Through an Ideal Contact Approaching the Schottky-Mott Limit

The advancement of flexible electronics necessitates low-power and high-gain organic transistors endowed with the capability to amplify feeble signals, meeting the demands of signal processing and transmission. Despite a myriad of endeavors, the intrinsic gain (Ai) of organic transistors at low supply voltage is conditioned by extrinsic losses attributable to imperfections at the electrical contact. Here, we push the metal-organic semiconductor contact close to the ideal Schottky-Mott model through a blade-coating-induced meniscus extension method, which allows the growth of organic single-crystalline films on multiple and uneven electrode heterointerfaces. Using this approach, our transistor manifests an impeccable gate electrostatic tunability with an ideal subthreshold swing (SS) of 59.6 mV dec-1 and a low average SS of 84.2 mV dec-1 over six decades of current, yielding a high Ai of 1.35 × 105, which is comparable with the reported champion organic thin-film transistors. As a result, an amplifier based on the transistors can operate normally at an extremely low dynamic power consumption of 33.2 pW and reach an ultrahigh voltage gain of 1590 V/V at a low voltage of 5 V. Our study promises to usher in low-power organic electronics reaching the bounds of physical performance.

Principles and Applications of Two-Dimensional Semiconductor Material Devices for Reconfigurable Electronics

With the advances in edge computing and artificial intelligence, the demands of multifunctional electronics with large area efficiency are increased. As the scaling down of the conventional transistor is restricted by physical limits, reconfigurable electronics are developed to promote the functional integration of integrated circuits. Reconfigurable electronics refer to electronics with switchable functionalities, including reconfigurable logic operation functionalities and reconfigurable responses to electrical or optical signals. Reconfigurable electronics integrate data-processing capabilities with reduced size. Two-dimensional (2D) semiconductor materials exhibit excellent modulation capabilities through electrical and optical signals, and structural designs of 2D material devices achieve versatile and switchable functionalities. 2D semiconductors have great potential to develop advanced reconfigurable electronics. Recent years witnessed the rapid development of 2D material devices for reconfigurable electronics. This work focuses on the working principles of 2D material devices used for reconfigurable electronics, discusses applications of 2D-material-based reconfigurable electronics in logic operation and artificial intelligence, and further provides a future outlook for the development of reconfigurable electronics based on 2D material devices.

Controllable spin rectification behavior of vertical and lateral VSe2/WSe2 heterojunction Schottky diodes

Heterojunctions (HJs) based on two-dimensional (2D) transition metal dichalcogenides are considered promising candidates for next-generation electronic and optoelectronic devices. Here, vertical (V-type) and lateral (L-type) HJ diodes based on metallic 1T-VSe2 and semiconducting 2H-WSe2 with out-of-plane and in-plane contacts are designed. First-principles quantum transport simulations reveal that both V- and L-type VSe2/WSe2 HJ diodes form p-type Schottky contacts. Under zero gate voltage, V-type VSe2/WSe2 HJ Schottky diodes exhibit superior spin rectification behavior compared to L-type, with rectification ratios approaching 109 and 106, respectively. At 300 K, the ideality factor of the V-type diode is lower than that of the L-type and reaches the ideal state at 478 and 510 K, respectively. Notably, positive gate voltage can reverse the rectification direction in both diodes and weaken the rectifying effect in V-type devices. Conversely, negative gate voltage significantly increases the current in both diodes and enhances the rectification ratio of the L-type device to 109. These findings provide insights into the spin-dependent rectification behavior of V- and L-type VSe2/WSe2 HJs in Schottky diodes, offering theoretical guidance for exploring magnetic nanoscale devices based on 2D materials.

Molecular Reconfiguration of Disordered Tellurium Oxide Transistors with Biomimetic Spectral Selectivity

Reconfigurable devices with field-effect transistor features and neuromorphic behaviors are promising for enhancing data processing capability and reducing power consumption in next-generation semiconductor platforms. However, commonly used 2D materials for reconfigurable devices require additional modulation terminals and suffer from complex and stringent operating rules to obtain specific functionalities. Here, a p-type disordered tellurium oxide is introduced that realizes dual-mode reconfigurability as a logic transistor and a neuromorphic device. Due to the disordered film surface, the enhanced adsorption of oxygen molecules and laser-induced desorption concurrently regulate the carrier concentration in the channel. The device exhibits high-performance p-type characteristics with a field-effect hole mobility of 10.02 cm2 V-1 s-1 and an Ion/Ioff ratio exceeding 106 in the transistor mode. As a neuromorphic device, the vision system exhibits biomimetic bee vision, explicitly responding to the blue-to-ultraviolet light. Finally, in-sensor denoising and invisible image recognition in static and dynamic scenarios are achieved.

Ultralow-Power Circuit and Sensing Applications Based on Subthermionic Threshold Switching Transistors

The most recent breakthrough in state-of-the-art electronics and optoelectronics involves the adoption of steep-slope field-effect transistors (FETs), promoting sub-60 mV/dec subthreshold swing (SS) at ambient temperature, effectively overcoming "Boltzmann limit" to minimize power consumption. Here, a series integration of nanoscale copper-based resistive-filamentary threshold switch (TS) with the IGZO channel-based FET is used to develop a TS-FET, in which the turn-on characteristics exhibit an abrupt transition over five decades, with an extremely low SS of 7 mV/dec, a high on/off ratio (>109), and ultralow leakage current (40-fold decrease), ensuring excellent repeatability and device yield. Unlike previous device-centric studies, this work highlights potential circuit applications (logic-inverter, pulse-sensor amplification, and photodetector) based on TS-FET. The sharp transition behavior of TS-FET enables the establishment of logic inverters with a high voltage gain of ≈800, with a circuit-level demonstration achieving a bias-independent record-high intrinsic gain (>1000). A wearable pulse sensor integrated with an amplifier circuit ensured the precise amplification of electrophysical signals by 450 times. In addition, the application of a TS-FET-based photodetector features high responsivity (1.08 × 104 mA/W) and detectivity (1.03 × 1020 Jones). The low-power strategy of TS-FETs is promising for the development of energy-efficient integrated circuits alongside sensor-interconnected biomedical applications in wearable technology.

Multibarrier Collaborative Modulation Devices with Ultra-High Logic Operation Density

The demands for highly miniaturized and multifunctional electronics are rapidly increasing. As scaling-down processes of transistors are restricted by physical limits, reconfigurable electronics with switchable operation functions for different tasks are developed for higher function integration based on split- or vertical-dual-gate structures. To promote the present reconfigurable electronics and exceed the function integration limit, the critical issue is to integrate complex operations into simple circuit forms by establishing more control dimensions. This work proposes a multibarrier collaborative (MBC) modulation architecture to increase the control dimension by multiple forms of potential barriers and achieves combinational and reconfigurable logic operations by a single MBC device. The MBC architecture exhibits ultrahigh logic operation density, including 58.8% area reduction for multiplexer operations and 71.4% area reduction for 4-logic reconfigurable operations. Besides, a hardware security module composed of 4 MBC devices implementing 8 types of logic operations is demonstrated. This work reveals an effective design of function integration for next-generation electronics.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5 V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60 mV dec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

The Roadmap of 2D Materials and Devices Toward Chips

Due to the constraints imposed by physical effects and performance degradation, silicon-based chip technology is facing certain limitations in sustaining the advancement of Moore's law. Two-dimensional (2D) materials have emerged as highly promising candidates for the post-Moore era, offering significant potential in domains such as integrated circuits and next-generation computing. Here, in this review, the progress of 2D semiconductors in process engineering and various electronic applications are summarized. A careful introduction of material synthesis, transistor engineering focused on device configuration, dielectric engineering, contact engineering, and material integration are given first. Then 2D transistors for certain electronic applications including digital and analog circuits, heterogeneous integration chips, and sensing circuits are discussed. Moreover, several promising applications (artificial intelligence chips and quantum chips) based on specific mechanism devices are introduced. Finally, the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed, and potential development pathways or roadmaps are further speculated and outlooked.

Contributions of Light to Novel Logic Concepts Using Optoelectronic Materials

Instead of the current method of transmitting voltage or current signals in electronic circuit operation, light offers an alternative to conventional logic, allowing for the implementation of new logic concepts through interaction with light. This manuscript examines the use of light in implementing new logic concepts as an alternative to traditional logic circuits and as a future technology. This article provides an overview of how to implement logic operations using light rather than voltage or current signals using optoelectronic materials such as 2D materials, metal-oxides, carbon structures, polymers, small molecules, and perovskites. This review covers the various technologies and applications of using light to dope devices, implement logic gates, control logic circuits, and generate light as an output signal. Recent research on logic and the use of light to implement new functions is summarized. This review also highlights the potential of optoelectronic logic for future technological advancements.

Two-dimensional HfS2-ZrS2 lateral heterojunction FETs with high rectification and photocurrent

Multifunctional devices are an indispensable choice to fulfil the increasing demand for miniaturized and integrated circuit systems. However, bulk material-based devices encounter the challenge of miniaturized all-in-one systems with multiple functions. In this study, we designed a field effect transistor (FET) based on a monolayer HfS2-ZrS2 lateral heterojunction. It possesses simultaneous and obvious rectifying behavior and photodetection characteristics in the visible light region, such as the rectification ratio of ∼1012, photocurrent density of 13.3 nA m-1, responsivity of 57 mA W-1, and extinction ratio of 108. Notably, the rectification ratio of the single-gate FET is larger than that of the dual-gate FET under the negative gate voltage. These results indicate that monolayer lateral heterojunction-based FETs can provide an effective route to integrate rectifying and photodetection functions in single optoelectronic nanodevices.

Wide-range and area-selective threshold voltage tunability in ultrathin indium oxide transistors

The scaling of transistors with thinner channel thicknesses has led to a surge in research on two-dimensional (2D) and quasi-2D semiconductors. However, modulating the threshold voltage (VT) in ultrathin transistors is challenging, as traditional doping methods are not readily applicable. In this work, we introduce a optical-thermal method, combining ultraviolet (UV) illumination and oxygen annealing, to achieve broad-range VT tunability in ultrathin In2O3. This method can achieve both positive and negative VT tuning and is reversible. The modulation of sheet carrier density, which corresponds to VT shift, is comparable to that obtained using other doping and capacitive charging techniques in other ultrathin transistors, including 2D semiconductors. With the controllability of VT, we successfully demonstrate the realization of depletion-load inverter and multi-state logic devices, as well as wafer-scale VT modulation via an automated laser system, showcasing its potential for low-power circuit design and non-von Neumann computing applications.

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors

Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal-oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe₂) are fabricated. A high on-off ratio of 10⁸ and 10⁶, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of V_T-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the V_T-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.

2D materials readiness for the transistor performance breakthrough

As the size of the transistor scales down, this strategy has confronted challenges because of the fundamental limits of silicon materials. Besides, more and more energy and time are consumed by the data transmission out of transistor computing because of the speed mismatching between the computing and memory. To meet the energy efficiency demands of big data computing, the transistor should have a smaller feature size and store data faster to overcome the energy burden of computing and data transfer. Electron transport in two-dimensional (2D) materials is constrained within a 2D plane and different materials are assembled by the van der Waals force. Owning to the atomic thickness and dangling-bond-free surface, 2D materials have demonstrated advantages in transistor scaling-down and heterogeneous structure innovation. In this review, from the performance breakthrough of 2D transistors, we discuss the opportunities, progress and challenges of 2D materials in transistor applications.

Two-dimensional MoSi2As4-based field-effect transistors integrating switching and gas-sensing functions

Multifunctional nanoscale devices integrating multiple functions are of great importance for meeting the requirements of next-generation electronics. Herein, using first-principles calculations, we propose multifunctional devices based on the two-dimensional monolayer MoSi₂As₄, where a single-gate field-effect transistor (FET) and FET-type gas sensor are integrated. After introducing the optimizing strategies, such as underlap structures and dielectrics with a high dielectric constant (κ), we designed a 5 nm gate-length MoSi₂As₄ FET, whose performance fulfilled the key criteria of the International Technology Roadmap for Semiconductors (ITRS) for high-performance semiconductors. Under the joint adjustment of the underlap structure and high-κ dielectric material, the on/off ratio of the 5 nm gate-length FET reached up to 1.38 × 10⁴. In addition, driven by the high-performance FET, the MoSi₂As₄-based FET-type gas sensor showed a sensitivity of 38% for NH₃ and 46% for NO_2. Moreover, the weak interaction between NH₃ (NO₂) and MoSi₂As₄ favored the recycling of the sensor. Furthermore, the sensitivity of the sensor could be effectively improved by the gate voltage, and was increased up to 67% (74%) for NH₃ (NO₂). Our work provides theoretical guidance for the fabrication of multifunctional devices combining a high-performance FET and sensitive gas sensor.

Combination of Polymer Gate Dielectric and Two-Dimensional Semiconductor for Emerging Field-Effect Transistors

Two-dimensional (2D) materials are considered attractive semiconducting layers for emerging field-effect transistors owing to their unique electronic and optoelectronic properties. Polymers have been utilized in combination with 2D semiconductors as gate dielectric layers in field-effect transistors (FETs). Despite their distinctive advantages, the applicability of polymer gate dielectric materials for 2D semiconductor FETs has rarely been discussed in a comprehensive manner. Therefore, this paper reviews recent progress relating to 2D semiconductor FETs based on a wide range of polymeric gate dielectric materials, including (1) solution-based polymer dielectrics, (2) vacuum-deposited polymer dielectrics, (3) ferroelectric polymers, and (4) ion gels. Exploiting appropriate materials and corresponding processes, polymer gate dielectrics have enhanced the performance of 2D semiconductor FETs and enabled the development of versatile device structures in energy-efficient ways. Furthermore, FET-based functional electronic devices, such as flash memory devices, photodetectors, ferroelectric memory devices, and flexible electronics, are highlighted in this review. This paper also outlines challenges and opportunities in order to help develop high-performance FETs based on 2D semiconductors and polymer gate dielectrics and realize their practical applications.

Junctionless Electric-Double-Layer MoS2 Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

Junctionless transistors are suitable for sub-3 nm applications because of their extremely simple structure and high electrical performance, which compensate for short-channel effects. Two-dimensional semiconductor transition-metal dichalcogenide materials, such as MoS₂, may also resolve technical and fundamental issues for Si-based technology. Here, we present the first junctionless electric-double-layer field-effect transistor with an electrostatically highly doped 5 nm thick MoS₂ channel. A double-gated MoS₂ transistor with an ionic-liquid top gate and a conventional bottom gate demonstrated good transfer characteristics with a 10⁴ on-off current ratio, a 70 mV dec^-1 subthreshold swing at a 0 V bottom-gate bias, and drain-current versus top-gate-voltage characteristics were shifted left significantly with increasing bottom-gate bias due to an electrostatically increased overall charge carrier concentration in the MoS₂ channel. When a bottom-gate bias of 80 V was applied, a shoulder and two clear peak features were identified in the transconductance and its derivative, respectively; this outcome is typical of Si-based junctionless transistors. Furthermore, the decrease in electron mobility induced by a transverse electric field was reduced with increasing bottom-gate bias. Numerical simulations and analytical models were used to support these findings, which clarify the operation of junctionless MoS₂ transistors with an electrostatically highly doped channel.

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors

2D semiconductors, such as molybdenum disulfide (MoS₂ ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS₂ film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS₂ field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS₂ logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.

Tuning Threshold Voltage of Electrolyte-Gated Transistors by Binary Ion Doping

Electrolyte-gated transistors (EGTs) operating at low voltages have attracted significant attention in widespread applications, including neuromorphic devices, nonvolatile memories, chemical/biosensors, and printed electronics. To increase the practicality of the EGTs in electronic circuits, systematic control of threshold voltage (Vth), which determines the power consumption and noise margin of the circuits, is essential. In this study, we present a simple strategy for systematically tuning Vth to almost half of the operating potential range of the EGT by controlling the electrochemical doping of electrolyte ions into organic p-type semiconductors. The type of anion in the ionogel determines Vth as well as other transistor characteristics, such as the subthreshold swing and mobility, because the positive hole carriers are the majority carriers. More importantly, Vth can be finely controlled by binary anion doping using ionogels with two anions with varying molar fractions at a fixed cation. In addition, the binary anion doping successfully controls the inversion characteristics of ion-gated inverters. As unlimited combinations of ion pairs are possible for ionogels, this study opens a route for controlling the device characteristics to expand the practicality and applicability of ionogel-based EGTs for next-generation ionic/electronic devices.

Evolution Application of Two-Dimensional MoS2-Based Field-Effect Transistors

High-performance and low-power field-effect transistors (FETs) are the basis of integrated circuit fields, which undoubtedly require researchers to find better film channel layer materials and improve device structure technology. MoS₂ has recently shown a special two-dimensional (2D) structure and superior photoelectric performance, and it has shown new potential for next-generation electronics. However, the natural atomic layer thickness and large specific surface area of MoS₂ make the contact interface and dielectric interface have a great influence on the performance of MoS₂ FET. Thus, we focus on its main performance improvement strategies, including optimizing the contact behavior, regulating the conductive channel, and rationalizing the dielectric layer. On this basis, we summarize the applications of 2D MoS₂ FETs in key and emerging fields, specifically involving logic, RF circuits, optoelectronic devices, biosensors, piezoelectric devices, and synaptic transistors. As a whole, we discuss the state-of-the-art, key merits, and limitations of each of these 2D MoS₂-based FET systems, and prospects in the future.

Carrier-Transport Mechanism in Organic Antiambipolar Transistors Unveiled by Operando Photoemission Electron Microscopy

Organic antiambipolar transistors (AATs) have partially overlapped p-n junctions. At room temperature, this p-n junction induces a negative differential transconductance in an AAT. However, the detailed carrier-transport mechanism remains unclear. Herein, an operando photoemission electron microscopy is used to tackle this issue owing to the technique's ability to visualize conductive electrons in real time during transistor operation. Notably, it is observed that when the AAT is on, a depletion layer forms at the lateral p-n junction. The visualized depletion layer shows that both p- and n-type channels have pinch-off states in the gate voltage range when the AAT is in on state. The steep potential gradient at the lateral p-n interface enhances the electron conduction from n-type to p-type semiconductor. Another significant finding is that most electrons are considered to recombine with the accumulated holes in the p-type semiconductor, affording the reduction of photoemission intensity by ≈80%. This technique provides a thorough understanding of carrier transport in AATs, further improving the device performance.

Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning

Electronic devices based on two-dimensional semiconductors suffer from limited electrical stability because charge carriers originating from the semiconductors interact with defects in the surrounding insulators. In field-effect transistors, the resulting trapped charges can lead to large hysteresis and device drifts, particularly when common amorphous gate oxides (such as silicon or hafnium dioxide) are used, hindering stable circuit operation. Here, we show that device stability in graphene-based field-effect transistors with amorphous gate oxides can be improved by Fermi-level tuning. We deliberately tune the Fermi level of the channel to maximize the energy distance between the charge carriers in the channel and the defect bands in the amorphous aluminium gate oxide. Charge trapping is highly sensitive to the energetic alignment of the Fermi level of the channel with the defect band in the insulator, and thus, our approach minimizes the amount of electrically active border traps without the need to reduce the total number of traps in the insulator.

Growth of Tellurium Nanobelts on h-BN for p-type Transistors with Ultrahigh Hole Mobility

The lack of stable p-type van der Waals (vdW) semiconductors with high hole mobility severely impedes the step of low-dimensional materials entering the industrial circle. Although p-type black phosphorus (bP) and tellurium (Te) have shown promising hole mobilities, the instability under ambient conditions of bP and relatively low hole mobility of Te remain as daunting issues. Here we report the growth of high-quality Te nanobelts on atomically flat hexagonal boron nitride (h-BN) for high-performance p-type field-effect transistors (FETs). Importantly, the Te-based FET exhibits an ultrahigh hole mobility up to 1370 cm² V^-1 s^-1 at room temperature, that may lay the foundation for the future high-performance p-type 2D FET and metal-oxide-semiconductor (p-MOS) inverter. The vdW h-BN dielectric substrate not only provides an ultra-flat surface without dangling bonds for growth of high-quality Te nanobelts, but also reduces the scattering centers at the interface between the channel material and the dielectric layer, thus resulting in the ultrahigh hole mobility .

Electrically Reconfigurable Organic Logic Gates: A Promising Perspective on a Dual-Gate Antiambipolar Transistor

Electrically reconfigurable organic logic circuits are promising candidates for realizing new computation architectures, such as artificial intelligence and neuromorphic devices. In this study, multiple logic gate operations are attained based on a dual-gate organic antiambipolar transistor (DG-OAAT). The transistor exhibits a Λ-shaped transfer curve, namely, a negative differential transconductance at room temperature. It is important to note that the peak voltage of the drain current is precisely tuned by three input signals: bottom-gate, top-gate, and drain voltages. This distinctive feature enables multiple logic gate operations with "only a single DG-OAAT," which are not obtainable in conventional transistors. Five logic gate operations, which correspond to AND, OR, NAND, NOR, and XOR, are demonstrated by adjusting the bottom-gate and top-gate voltages. Moreover, varying the drain voltage makes it possible to reversibly switch two logic gates, e.g., NAND/NOR and OR/XOR. In addition, the DG-OAATs show a high degree of stability and reliability. The logic gate operations are observed even months later. The hysteresis in the transfer curves is also negligible. Thus, the device concept is promising for realizing multifunctional logic circuits with a simple transistor configuration. Hence, these findings are expected to surpass the current limitations in complementary metal-oxide-semiconductor devices.

2D Heterostructures for Ubiquitous Electronics and Optoelectronics: Principles, Opportunities, and Challenges

A grand family of two-dimensional (2D) materials and their heterostructures have been discovered through the extensive experimental and theoretical efforts of chemists, material scientists, physicists, and technologists. These pioneering works contribute to realizing the fundamental platforms to explore and analyze new physical/chemical properties and technological phenomena at the micro-nano-pico scales. Engineering 2D van der Waals (vdW) materials and their heterostructures via chemical and physical methods with a suitable choice of stacking order, thickness, and interlayer interactions enable exotic carrier dynamics, showing potential in high-frequency electronics, broadband optoelectronics, low-power neuromorphic computing, and ubiquitous electronics. This comprehensive review addresses recent advances in terms of representative 2D materials, the general fabrication methods, and characterization techniques and the vital role of the physical parameters affecting the quality of 2D heterostructures. The main emphasis is on 2D heterostructures and 3D-bulk (3D) hybrid systems exhibiting intrinsic quantum mechanical responses in the optical, valley, and topological states. Finally, we discuss the universality of 2D heterostructures with representative applications and trends for future electronics and optoelectronics (FEO) under the challenges and opportunities from physical, nanotechnological, and material synthesis perspectives.

Scalable Van der Waals Encapsulation by Inorganic Molecular Crystals

Encapsulation is critical for devices to guarantee their stability and reliability. It becomes an even more essential requirement for devices based on 2D materials with atomic thinness and far inferior stability compared to their bulk counterparts. Here a general van der Waals (vdW) encapsulation method for 2D materials using Sb₂ O₃ layer of inorganic molecular crystal fabricated via thermal evaporation deposition is reported. It is demonstrated that such a scalable encapsulation method not only maintains the intrinsic properties of typical air-susceptible 2D materials due to their vdW interactions but also remarkably improves their environmental stability. Specifically, the encapsulated black phosphorus (BP) exhibits greatly enhanced structural stability of over 80 days and more sustaining-electrical properties of 19 days, while the bare BP undergoes degradation within hours. Moreover, the encapsulation layer can be facilely removed by sublimation in vacuum without damaging the underlying materials. This scalable encapsulation method shows a promising pathway to effectively enhance the environmental stability of 2D materials, which may further boost their practical application in novel (opto)electronic devices.