Transferred metal gate to 2D semiconductors for sub-1 V operation and near ideal subthreshold slope

J-MISFET Hybrid Dual-Gate Switching Device for Multifunctional Optoelectronic Logic Gate Applications

High-performance and low operating voltage are becoming increasingly significant device parameters to meet the needs of future integrated circuit (IC) processors and ensure their energy-efficient use in upcoming mobile devices. In this study, we suggest a hybrid dual-gate switching device consisting of the vertically stacked junction and metal-insulator-semiconductor (MIS) gate structure, named J-MISFET. It shows excellent device performances of low operating voltage (<0.5 V), drain current ON/OFF ratio (∼4.7 × 105), negligible hysteresis window (<0.5 mV), and near-ideal subthreshold slope (SS) (60 mV/dec), making it suitable for low-power switching operation. Furthermore, we investigated the switchable NAND/NOR logic gate operations and the photoresponse characteristics of the J-MISFET under the small supply voltage (0.5 V). To advance the applications further, we successfully demonstrated an integrated optoelectronic security logic system comprising 2-electric inputs (for encrypted data) and 1-photonic input signal (for password key) as a hardware security device for data protection. Thus, we believe that our J-MISFET, with its heterogeneous hybrid gate structures, will illuminate the path toward future device configurations for next-generation low-power electronics and multifunctional security logic systems in a data-driven society.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5 V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60 mV dec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

Engineering van der Waals Contacts by Interlayer Dipoles

Tuning the interfacial Schottky barrier with van der Waals (vdW) contacts is an important solution for two-dimensional (2D) electronics. Here we report that the interlayer dipoles of 2D vdW superlattices (vdWSLs) can be used to engineer vdW contacts to 2D semiconductors. A bipolar WSe2 with Ba6Ta11S28 (BTS) vdW contact was employed to exhibit this strategy. Strong interlayer dipoles can be formed due to charge transfer between the Ba3TaS5 and TaS2 layers. Mechanical exfoliation breaks the superlattice and produces two distinguished surfaces with TaS2 and Ba3TaS5 terminations. The surfaces thus have opposite surface dipoles and consequently different work functions. Therefore, all the devices fall into two categories in accordance with the rectifying direction, which were verified by electrical measurements and scanning photocurrent microscopy. The growing vdWSL family along with the addition surface dipoles enables prospective vdW contact designs and have practical application in nanoelectronics and nano optoelectronics.

Direct Characterization of Buried Interfaces in 2D/3D Heterostructures Enabled by GeO2 Release Layer

Inconsistent interface control in devices based on two-dimensional materials (2DMs) has limited technological maturation. Astounding variability of 2D/three-dimensional (2D/3D) interface properties has been reported, which has been exacerbated by the lack of direct investigations of buried interfaces commonly found in devices. Herein, we demonstrate a new process that enables the assembly and isolation of device-relevant heterostructures for buried interface characterization. This is achieved by implementing a water-soluble substrate (GeO2), which enables deposition of many materials onto the 2DM and subsequent heterostructure release by dissolving the GeO2 substrate. Here, we utilize this novel approach to compare how the chemistry, doping, and strain in monolayer MoS2 heterostructures fabricated by direct deposition vary from those fabricated by transfer techniques to show how interface properties differ with the heterostructure fabrication method. Direct deposition of thick Ni and Ti films is found to react with the monolayer MoS2. These interface reactions convert 50% of MoS2 into intermetallic species, which greatly exceeds the 10% conversion reported previously and 0% observed in transfer-fabricated heterostructures. We also measure notable differences in MoS2 carrier concentration depending on the heterostructure fabrication method. Direct deposition of thick Au, Ni, and Al2O3 films onto MoS2 increases the hole concentration by >1012 cm-2 compared to heterostructures fabricated by transferring MoS2 onto these materials. Thus, we demonstrate a universal method to fabricate 2D/3D heterostructures and expose buried interfaces for direct characterization.

Engineering electrode interfaces for telecom-band photodetection in MoS2/Au heterostructures via sub-band light absorption

Transition metal dichalcogenide (TMD) layered semiconductors possess immense potential in the design of photonic, electronic, optoelectronic, and sensor devices. However, the sub-bandgap light absorption of TMD in the range from near-infrared (NIR) to short-wavelength infrared (SWIR) is insufficient for applications beyond the bandgap limit. Herein, we report that the sub-bandgap photoresponse of MoS2/Au heterostructures can be robustly modulated by the electrode fabrication method employed. We observed up to 60% sub-bandgap absorption in the MoS2/Au heterostructure, which includes the hybridized interface, where the Au layer was applied via sputter deposition. The greatly enhanced absorption of sub-bandgap light is due to the planar cavity formed by MoS2 and Au; as such, the absorption spectrum can be tuned by altering the thickness of the MoS2 layer. Photocurrent in the SWIR wavelength range increases due to increased absorption, which means that broad wavelength detection from visible toward SWIR is possible. We also achieved rapid photoresponse (~150 µs) and high responsivity (17 mA W-1) at an excitation wavelength of 1550 nm. Our findings demonstrate a facile method for optical property modulation using metal electrode engineering and for realizing SWIR photodetection in wide-bandgap 2D materials.

Forming Stable van der Waals Contacts between Metals and 2D Semiconductors

High-performing 2D electrical and optical devices can be realized by forming an ideal van der Waals (vdW) metal contact with weak interactions and stable interface states. However, the methods for applying metal contacts while avoiding damage from metal deposition present challenges in realizing a uniform, stable vdW interface. To overcome this problem, this study develops a method for forming vdW contacts using a sacrificial Se buffer layer. This study explores this method by investigating the difference in the Schottky barrier height between the vdW metal contact deposited using a buffer layer, a transferred metal contact, and a conventional directly deposited metal contact using rectification and photovoltaic characteristics of a Schottky diode structure with graphite. Evidently, the Se buffer layer method forms the most stable and ideal vdW contact while preventing Fermi-level pinning. A tungsten diselenide Schottky diode fabricated using these vdW contacts with Au and graphite as the top and bottom electrodes, respectively, exhibits excellent operation with an ideality factor of ≈1, an on/off ratio of > 107 , and coherent properties. Additionally, when using only the vdW Au contact, the electrical and optical properties of the device can be minutely modulated by changing the structure of the Schottky diode.

Multifunctional Magnetic Oxide-MoS2 Heterostructures on Silicon

Correlated oxides and related heterostructures are intriguing for developing future multifunctional devices by exploiting their exotic properties, but their integration with other materials, especially on Si-based platforms, is challenging. Here, van der Waals heterostructures of La0.7 Sr0.3 MnO3 (LSMO) , a correlated manganite perovskite, and MoS2 are demonstrated on Si substrates with multiple functions. To overcome the problems due to the incompatible growth process, technologies involving freestanding LSMO membranes and van der Waals force-mediated transfer are used to fabricate the LSMO-MoS2 heterostructures. The LSMO-MoS2 heterostructures exhibit a gate-tunable rectifying behavior, based on which metal-semiconductor field-effect transistors (MESFETs) with on-off ratios of over 104 can be achieved. The LSMO-MoS2 heterostructures can function as photodiodes displaying considerable open-circuit voltages and photocurrents. In addition, the colossal magnetoresistance of LSMO endows the LSMO-MoS2 heterostructures with an electrically tunable magnetoresponse at room temperature. This work not only proves the applicability of the LSMO-MoS2 heterostructure devices on Si-based platform but also demonstrates a paradigm to create multifunctional heterostructures from materials with disparate properties.

Optimization of Subthreshold Swing and Hysteresis in Hf0.5Zr0.5O2-Based MoS2 Negative Capacitance Field-Effect Transistors by Modulating Capacitance Matching

Negative capacitance field effect transistors made of Hf_0.5Zr_0.5O₂ (HZO) are one of the most promising candidates for low-power-density devices because of the extremely steep subthreshold swing and high open-state currents resulting from the addition of ferroelectric materials in the gate dielectric layer. In this paper, HZO thin films were prepared by magnetron sputtering combined with rapid thermal annealing. Their ferroelectric properties were adjusted by changing the annealing temperature and the thickness of HZO. Two-dimensional MoS₂ back-gate negative capacitance field-effect transistors (NCFETs) based on HZO were prepared as well. Different annealing temperatures, thicknesses of HZO thin films, and Al₂O₃ thicknesses were studied to achieve optimal capacitance matching, aiming to reduce both the subthreshold swing of the transistor and the hysteresis of the NCFET. The NCFET exhibits a minimum subthreshold swing as low as 27.9 mV/decade, negligible hysteresis (∼20 mV), and the I_ON/I_OFF of up to 1.58 × 10⁷. Moreover, a negative drain-induced barrier lowering effect and a negative differential resistance effect have been observed. This steep-slope transistor is compatible with standard CMOS manufacturing processes and attractive for 2D logic and sensor applications as well as future energy-efficient nanoelectronic devices with scaled power supplies.

All-Transfer Electrode Interface Engineering Toward Harsh-Environment-Resistant MoS2 Field-Effect Transistors

Nanoscale electronic devices that can work in harsh environments are in high demand for wearable, automotive, and aerospace electronics. Clean and defect-free interfaces are of vital importance for building nanoscale harsh-environment-resistant devices. However, current nanoscale devices are subject to failure in these environments, especially at defective electrode-channel interfaces. Here, harsh-environment-resistant MoS₂ transistors are developed by engineering electrode-channel interfaces with an all-transfer of van der Waals electrodes. The delivered defect-free, graphene-buffered electrodes keep the electrode-channel interfaces intact and robust. As a result, the as-fabricated MoS₂ devices have reduced Schottky barrier heights, leading to a very large on-state current and high carrier mobility. More importantly, the defect-free, hydrophobic graphene buffer layer prevents metal diffusion from the electrodes to MoS₂ and the intercalation of water molecules at the electrode-MoS₂ interfaces. This enables high resistances of MoS₂ devices with all-transfer electrodes to various harsh environments, including humid, oxidizing, and high-temperature environments, surpassing the devices with other kinds of electrodes. The work deepens the understanding of the roles of electrode-channel interfaces in nanoscale devices and provides a promising interface engineering strategy to build nanoscale harsh-environment-resistant devices.

Carrier Modulation in 2D Transistors by Inserting Interfacial Dielectric Layer for Area-Efficient Computation

2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area-efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe₂ ) field-effect transistors (FETs) via introducing hexagonal boron nitride (h-BN) as the interfacial dielectric layer is devised. By modulating the h-BN thickness, the carrier type of WSe₂ FETs has been switched from hole to electron. The ultrathin body of WSe₂ , combined with the effective polarity control, together contribute to the versatile single-transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. The unique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation.

Two-dimensional devices and integration towards the silicon lines

Despite technical efforts and upgrades, advances in complementary metal-oxide-semiconductor circuits have become unsustainable in the face of inherent silicon limits. New materials are being sought to compensate for silicon deficiencies, and two-dimensional materials are considered promising candidates due to their atomically thin structures and exotic physical properties. However, a potentially applicable method for incorporating two-dimensional materials into silicon platforms remains to be illustrated. Here we try to bridge two-dimensional materials and silicon technology, from integrated devices to monolithic 'on-silicon' (silicon as the substrate) and 'with-silicon' (silicon as a functional component) circuits, and discuss the corresponding requirements for material synthesis, device design and circuitry integration. Finally, we summarize the role played by two-dimensional materials in the silicon-dominated semiconductor industry and suggest the way forward, as well as the technologies that are expected to become mainstream in the near future.

A general one-step plug-and-probe approach to top-gated transistors for rapidly probing delicate electronic materials

The miniaturization of silicon-based electronics has motivated considerable efforts in exploring new electronic materials, including two-dimensional semiconductors and halide perovskites, which are usually too delicate to maintain their intrinsic properties during the harsh device fabrication steps. Here we report a convenient plug-and-probe approach for one-step simultaneous van der Waals integration of high-k dielectrics and contacts to enable top-gated transistors with atomically clean and electronically sharp dielectric and contact interfaces. By applying the plug-and-probe top-gate transistor stacks on two-dimensional semiconductors, we demonstrate an ideal subthreshold swing of 60 mV per decade. Using this approach on delicate lead halide perovskite, we realize a high-k top-gate CsPbBr₃ transistor with a low operating voltage and a very high two-terminal field-effect mobility of 32 cm² V^-1 s^-1. This approach can be extended to centimetre-scale MoS₂ and perovskite and generate top-gated transistor arrays, offering a rapid and convenient way of accessing intrinsic properties of delicate emerging materials.

Strain Releasing of Flexible 2D Electronics through van der Waals Sliding Contact

Two-dimensional (2D) materials have demonstrated promising potential for flexible electronics, owning to their atomic thin body thickness and dangling-bond-free surface. Here, we report a sliding contact device structure for efficient strain releasing. By fabricating a weakly coupled metal-2D junction with a van der Waals (vdW) gap in between, the applied strain could be effectively released through their interface sliding; hence minimized strain is transferred to the 2D lattice. Therefore, we observed stable device behavior with electrodes stretching over 110%, much higher than 2D devices using evaporated metal contacts. Furthermore, through multicycle straining-releasing measurements, we found the electrodes still form intimate contact with nearly constant contact resistance during sliding, confirming the optimization of device flexibility and electrical properties at the same time. Finally, we demonstrate this vdW sliding contact is a general device geometry and could be well-extended to various 2D or 3D bulk materials, leading to devices with much higher strain tolerance.

The floating body effect of a WSe2 transistor with volatile memory performance

The floating body effect in Meta-Stable-Dip RAM (MSDRAM) has been broadly employed in implementing single-transistor capacitor-less (1T0C) dynamic random access memory (DRAM) cells to break through the limitation of finite size reduction of peripheral capacitors. However, the majority of them were broadly demonstrated in conventional CMOS technology, while emerging semiconductor systems are rarely explored. Here, we creatively explore exfoliated multilayer tungsten diselenide (WSe₂) for the application of 1T0C DRAM, breaking the limitation of channel thickness in the traditional architecture. Through the comparison of the electrical characteristics among three dual-gate transistors with different lengths of top-gate, we demonstrated the essential role of the floating body effect in achieving the function of 1T0C DRAM displaying two distinct states that are differentiated by hole population within the floating body. Moreover, according to the analysis of in situ electrostatic force microscopy (EFM) measurements and theoretical calculation via density functional theory (DFT), the injection of holes through band-to-band (B2B) tunneling can be ascribed to the effectively electrostatic modulation. These consequences prove our innovative concept to achieve the function of 1T0C DRAM through employing the ML WSe₂, which is a vital step toward the breakthrough of the inherent limitations of DRAM cells.

High-performance, self-powered flexible MoS2 photodetectors with asymmetric van der Waals gaps

With an urgent demand for low-energy-consumption and wearable devices, it is desirable to find an easy, effective, and low-cost method to fabricate self-powered flexible photodetectors with simple configurations and high-performance. Self-powered photodetectors are normally fabricated based on either two different materials or the same material in contact with two different metal electrodes. Here, a flexible MoS₂ photodetector with the same Au electrodes was fabricated on a polyethylene terephthalate (PET) substrate which exhibits self-powered properties. To our knowledge, its configuration is the simplest, and the fabrication process is easy to implement. At a bias of 0 V, the photodetector exhibits a high responsivity of 431 mA W^-1, a short response/recovery time of 40 ms/40 ms, and excellent flexibility. Compared with those at a bias of 2 V, a dark current is sufficiently suppressed, and the response/recovery speed is significantly improved. It is found that the driving force of the self-powered photodetector is provided by the asymmetric Schottky barriers originating from the spontaneous generation of two van der Waals gaps with different widths. The asymmetric barriers exist stably at the interfaces between the 2D material and Au electrodes as further observed for ReS₂ or GaSe flakes, which show the generality of asymmetric Schottky barriers between the 2D material and Au electrodes. The discovery here thus gives a new way to generate asymmetric Schottky barriers and develop high-performance self-powered photodetectors.

Growth of wafer-scale graphene-hexagonal boron nitride vertical heterostructures with clear interfaces for obtaining atomically thin electrical analogs

Two-dimensional (2D) integrated circuits based on graphene (Gr) heterostructures have emerged as next-generation electronic devices. However, it is still challenging to produce high-quality and large-area Gr/hexagonal boron nitride (h-BN) vertical heterostructures with clear interfaces and precise layer control. In this work, a two-step metallic alloy-assisted epitaxial growth approach has been demonstrated for producing wafer-scale vertical hexagonal boron nitride/graphene (h-BN/Gr) heterostructures with clear interfaces. The heterostructures maintain high uniformity while scaling up and thickening. The layer number of both h-BN and graphene can be independently controlled by tuning the growth process. Furthermore, conductance measurements confirm that electrical hysteresis disappears on h-BN/Gr field-effect transistors, which is attributed to the h-BN dielectric surface. Our work blazes a trail toward next-generation graphene-based analog devices.

2D Heterostructures for Ubiquitous Electronics and Optoelectronics: Principles, Opportunities, and Challenges

A grand family of two-dimensional (2D) materials and their heterostructures have been discovered through the extensive experimental and theoretical efforts of chemists, material scientists, physicists, and technologists. These pioneering works contribute to realizing the fundamental platforms to explore and analyze new physical/chemical properties and technological phenomena at the micro-nano-pico scales. Engineering 2D van der Waals (vdW) materials and their heterostructures via chemical and physical methods with a suitable choice of stacking order, thickness, and interlayer interactions enable exotic carrier dynamics, showing potential in high-frequency electronics, broadband optoelectronics, low-power neuromorphic computing, and ubiquitous electronics. This comprehensive review addresses recent advances in terms of representative 2D materials, the general fabrication methods, and characterization techniques and the vital role of the physical parameters affecting the quality of 2D heterostructures. The main emphasis is on 2D heterostructures and 3D-bulk (3D) hybrid systems exhibiting intrinsic quantum mechanical responses in the optical, valley, and topological states. Finally, we discuss the universality of 2D heterostructures with representative applications and trends for future electronics and optoelectronics (FEO) under the challenges and opportunities from physical, nanotechnological, and material synthesis perspectives.