Floating gate memory-based monolayer MoS2 transistor with metal nanocrystals embedded in the gate dielectrics

Anti-Ambipolar Heterojunctions: Materials, Devices, and Circuits

Anti-ambipolar heterojunctions are vital in constructing high-frequency oscillators, fast switches, and multivalued logic (MVL) devices, which hold promising potential for next-generation integrated circuit chips and telecommunication technologies. Thanks to the strategic material design and device integration, anti-ambipolar heterojunctions have demonstrated unparalleled device and circuit performance that surpasses other semiconducting material systems. This review aims to provide a comprehensive summary of the achievements in the field of anti-ambipolar heterojunctions. First, the fundamental operating mechanisms of anti-ambipolar devices are discussed. After that, potential materials used in anti-ambipolar devices are discussed with particular attention to 2D-based, 1D-based, and organic-based heterojunctions. Next, the primary device applications employing anti-ambipolar heterojunctions, including anti-ambipolar transistors (AATs), photodetectors, frequency doublers, and synaptic devices, are summarized. Furthermore, alongside the advancements in individual devices, the practical integration of these devices at the circuit level, including topics such as MVL circuits, complex logic gates, and spiking neuron circuits, is also discussed. Lastly, the present key challenges and future research directions concerning anti-ambipolar heterojunctions and their applications are also emphasized.

Optical readout of charge carriers stored in a 2D memory cell of monolayer WSe2

Owing to their superior charge retaining and transport characteristics, 2D transition metal dichalcogenides are investigated for practical applications in various memory-cell structures. Herein, we fabricated a quasi-one-terminal 2D memory cell by partially depositing a WSe2 monolayer on an Au electrode, which can be manipulated to achieve efficient charge injection upon the application or removal of external bias. Furthermore, the amount of charge carriers stored in the memory cell could be optically probed because of its close correlation with the fluorescence efficiency of WSe2, allowing us to achieve an electron retention time of ∼300 s at the cryogenic temperature of 4 K. Accordingly, the simplified device structure and the non-contact optical readout of the stored charge carriers present new research opportunities for 2D memory cells in terms of both fundamental mechanism studies and practical development for integrated nanophotonic devices.

2D van der Waals Heterostructure with Tellurene Floating-Gate for Wide Range and Multi-Bit Optoelectronic Memory

Intensive research on optoelectronic memory (OEM) devices based on two-dimensional (2D) van der Waals heterostructures (vdWhs) is being conducted due to their distinctive advantages for electrical-optical writing and multilevel storage. These features make OEM a promising candidate for the logic of reconfigurable operations. However, the realization of nonvolatile OEM with broadband absorption (from visible to infrared) and a high switching ratio remains challenging. Herein, we report a nonvolatile OEM based on a heterostructure consisting of rhenium disulfide (ReS2), hexagonal boron nitride (hBN) and tellurene (2D Te). The 2D Te-based floating-gate (FG) device exhibits excellent performance metrics, including a high switching on/off ratio (∼106), significant endurance (>1000 cycles) and impressive retention (>104 s). In addition, the narrow band gap of 2D Te endows the device with broadband optical programmability from the visible to near-infrared regions at room temperature. Moreover, by applying different gate voltages, light wavelengths, and laser powers, multiple bits can be successfully generated. Additionally, the device is specifically designed to enable reconfigurable inverter logic circuits (including AND and OR gates) through controlled electrical and optical inputs. These significant findings demonstrate that the 2D vdWhs with a 2D Te FG are a valuable approach in the development of high-performance OEM devices.

Gate Dielectrics Integration for 2D Electronics: Challenges, Advances, and Outlook

2D semiconductors have emerged both as an ideal platform for fundamental studies and as promising channel materials in beyond-silicon field-effect-transistors due to their outstanding electrical properties and exceptional tunability via external field. However, the lack of proper dielectrics for 2D semiconductors has become a major roadblock for their further development toward practical applications. The prominent issues between conventional 3D dielectrics and 2D semiconductors arise from the integration and interface quality, where defect states and imperfections lead to dramatic deterioration of device performance. In this review article, the root causes of such issues are briefly analyzed and recent advances on some possible solutions, including various approaches of adapting conventional dielectrics to 2D semiconductors, and the development of novel dielectrics with van der Waals surface toward high-performance 2D electronics are summarized. Then, in the perspective, the requirements of ideal dielectrics for state-of-the-art 2D devices are outlined and an outlook for their future development is provided.

The Road for 2D Semiconductors in the Silicon Age

Continued reduction in transistor size can improve the performance of silicon integrated circuits (ICs). However, as Moore's law approaches physical limits, high-performance growth in silicon ICs becomes unsustainable, due to challenges of scaling, energy efficiency, and memory limitations. The ultrathin layers, diverse band structures, unique electronic properties, and silicon-compatible processes of 2D materials create the potential to consistently drive advanced performance in ICs. Here, the potential of fusing 2D materials with silicon ICs to minimize the challenges in silicon ICs, and to create technologies beyond the von Neumann architecture, is presented, and the killer applications for 2D materials in logic and memory devices to ease scaling, energy efficiency bottlenecks, and memory dilemmas encountered in silicon ICs are discussed. The fusion of 2D materials allows the creation of all-in-one perception, memory, and computation technologies beyond the von Neumann architecture to enhance system efficiency and remove computing power bottlenecks. Progress on the 2D ICs demonstration is summarized, as well as the technical hurdles it faces in terms of wafer-scale heterostructure growth, transfer, and compatible integration with silicon ICs. Finally, the promising pathways and obstacles to the technological advances in ICs due to the integration of 2D materials with silicon are presented.

Ultrafast Operation of 2D Heterostructured Nonvolatile Memory Devices Provided by the Strong Short-Time Dielectric Breakdown Strength of h-BN

Recently, the ultrafast operation (∼20 ns) of a two-dimensional (2D) heterostructured nonvolatile memory (NVM) device was demonstrated, attracting considerable attention. However, there is no consensus on its physical origin. In this study, various 2D NVM device structures are compared. First, we reveal that the hole injection at the metal/MoS₂ interface is the speed-limiting path in the NVM device with the access region. Therefore, MoS₂ NVM devices with a direct tunneling path between source/drain electrodes and the floating gate are fabricated by removing the access region. Indeed, a 50 ns program/erase operation is successfully achieved for devices with metal source/drain electrodes as well as graphite source/drain electrodes. This controlled experiment proves that an atomically sharp interface is not necessary for ultrafast operation, which is contrary to the previous literature. Finally, the dielectric breakdown strength (E_BD) of h-BN under short voltage pulses is examined. Since a high dielectric breakdown strength allows a large tunneling current, ultrafast operations can be achieved. Surprisingly, an E_BD = 26.1 MV/cm for h-BN is realized under short voltage pulses, largely exceeding the E_BD = ∼12 MV/cm from the direct current (DC) measurement. This suggests that the high E_BD of h-BN can be the physical origin of the ultrafast operation.

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS₂. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performed ex situ and transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.

Direct Charge Trapping Multilevel Memory with Graphdiyne/MoS2 Van der Waals Heterostructure

Direct charge trapping memory, a new concept memory without any dielectric, has begun to attract attention. However, such memory is still at the incipient stage, of which the charge-trapping capability depends on localized electronic states that originated from the limited surface functional groups. To further advance such memory, a material with rich hybrid states is highly desired. Here, a van der Waals heterostructure design is proposed utilizing the 2D graphdiyne (GDY) which possesses abundant hybrid states with different chemical groups. In order to form the desirable van der Waals coupling, the plasma etching method is used to rapidly achieve the ultrathin 2D GDY with smooth surface for the first time. With the plasma-treated 2D GDY as charge-trapping layer, a direct charge-trapping memory based on GDY/MoS2 is constructed. This bilayer memory is featured with large memory window (90 V) and high degree of modulation (on/off ratio around 8 × 107 ). Two operating mode can be achieved and data storage capability of 9 and 10 current levels can be obtained, respectively, in electronic and opto-electronic mode. This GDY/MoS2 memory introduces a novel application of GDY as rich states charge-trapping center and offers a new strategy of realizing high performance dielectric-free electronics, such as optical memories and artificial synaptic.

Atomically sharp interface enabled ultrahigh-speed non-volatile memory devices

The development of high-performance memory devices has played a key role in the innovation of modern electronics. Non-volatile memory devices have manifested high capacity and mechanical reliability as a mainstream technology; however, their performance has been hampered by low extinction ratio and slow operational speed. Despite substantial efforts to improve these characteristics, typical write times of hundreds of micro- or milliseconds remain a few orders of magnitude longer than that of their volatile counterparts. Here we demonstrate non-volatile, floating-gate memory devices based on van der Waals heterostructures with atomically sharp interfaces between different functional elements, achieving ultrahigh-speed programming/erasing operations in the range of nanoseconds with extinction ratio up to 10¹⁰. This enhanced performance enables new device capabilities such as multi-bit storage, thus opening up applications in the realm of modern nanoelectronics and offering future fabrication guidelines for device scale up.

Material and Device Structure Designs for 2D Memory Devices Based on the Floating Gate Voltage Trajectory

Two-dimensional heterostructures have been extensively investigated as next-generation nonvolatile memory (NVM) devices. In the past decade, drastic performance improvements and further advanced functionalities have been demonstrated. However, this progress is not sufficiently supported by the understanding of their operations, obscuring the material and device structure design policy. Here, detailed operation mechanisms are elucidated by exploiting the floating gate (FG) voltage measurements. Systematic comparisons of MoTe₂, WSe₂, and MoS₂ channel devices revealed that the tunneling behavior between the channel and FG is controlled by three kinds of current-limiting paths, i.e., tunneling barrier, 2D/metal contact, and p-n junction in the channel. Furthermore, the control experiment indicated that the access region in the device structure is required to achieve 2D channel/FG tunneling by preventing electrode/FG tunneling. The present understanding suggests that the ambipolar 2D-based FG-type NVM device with the access region is suitable for further realizing potentially high electrical reliability.

High-Performance Non-Volatile InGaZnO Based Flash Memory Device Embedded with a Monolayer Au Nanoparticles

Non-volatile memory (NVM) devices based on three-terminal thin-film transistors (TFTs) have gained extensive interest in memory applications due to their high retained characteristics, good scalability, and high charge storage capacity. Herein, we report a low-temperature (<100 °C) processed top-gate TFT-type NVM device using indium gallium zinc oxide (IGZO) semiconductor with monolayer gold nanoparticles (AuNPs) as a floating gate layer to obtain reliable memory operations. The proposed NVM device exhibits a high memory window (ΔVth) of 13.7 V when it sweeps from -20 V to +20 V back and forth. Additionally, the material characteristics of the monolayer AuNPs (floating gate layer) and IGZO film (semiconductor layer) are confirmed using transmission electronic microscopy (TEM), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) techniques. The memory operations in terms of endurance and retention are obtained, revealing highly stable endurance properties of the device up to 100 P/E cycles by applying pulses (±20 V, duration of 100 ms) and reliable retention time up to 104 s. The proposed NVM device, owing to the properties of large memory window, stable endurance, and high retention time, enables an excellent approach in futuristic non-volatile memory technology.

Design and tailoring of two-dimensional Schottky, PN and tunnelling junctions for electronics and optoelectronics

Owing to their superior carrier mobility, strong light-matter interactions, and flexibility at the atomically thin thickness, two-dimensional (2D) materials are attracting wide interest for application in electronic and optoelectronic devices, including rectifying diodes, transistors, memory, photodetectors, and light-emitting diodes. At the heart of these devices, Schottky, PN, and tunneling junctions are playing an essential role in defining device function. Intriguingly, the ultrathin thickness and unique van der Waals (vdW) interlayer coupling in 2D materials has rendered enormous opportunities for the design and tailoring of various 2D junctions, e.g. using Lego-like hetero-stacking, surface decoration, and field-effect modulation methods. Such flexibility has led to marvelous breakthroughs during the exploration of 2D electronics and optoelectronic devices. To advance further, it is imperative to provide an overview of existing strategies for the engineering of various 2D junctions for their integration in the future. Thus, in this review, we provide a comprehensive survey of previous efforts toward 2D Schottky, PN, and tunneling junctions, and the functional devices built from them. Though these junctions exhibit similar configurations, distinct strategies have been developed for their optimal figures of merit based on their working principles and functional purposes.

High-bandwidth light inputting multilevel photoelectric memory based on thin-film transistor with a floating gate of CsPbBr3/CsPbI3 blend quantum dots

The electronic-photonic convergent systems can overcome the data transmission bottleneck for microchips by enabling processor and memory chips with high-bandwidth optical input/output. However, current silicon-based electronic-photonic systems require various functional devices/components to convert high-bandwidth optical signals into electrical ones, thus making further integrations of sophisticated systems rather difficult. Here, we demonstrate thin-film transistor-based photoelectric memories employing CsPbBr₃/CsPbI₃ blend perovskite quantum dots (PQDs) as a floating gate, and multilevel memory cells are achieved under programming and erasing modes, respectively, by imputing high-bandwidth optical signals. For different bandwidth light input (i.e. 500-550, 575-650 and 675-750 nm) with the same intensity, three levels of programming window (i.e. 3.7, 1.9 and 0.8 V) and erasing window (i.e. -1.9, -0.6 and -0.1 V) are obtained under electrical pulses, respectively. This is because the blend PQDs have two different bandgaps, and different amounts of photo-generated carriers can be produced for different wavelength optical inputs. It is noticed that the 675-750 nm light inputs have no effects on both programming and erasing windows because of no photo-carriers generation. Four memory states are demonstrated, showing enough large gaps (1.12-5.61 V) between each other, good data retention and programming/erasing endurance. By inputting different optical signals, different memory states can be switched easily. Therefore, this work directly demonstrates high-bandwidth light inputting multilevel memory cells for novel electronic-photonic systems.

Tunable and nonvolatile multibit data storage memory based on MoTe2/boron nitride/graphene heterostructures through contact engineering

Heterostructures formed by stacking atomically thin two-dimensional materials are promising candidates for flash memory devices to achieve premium performances, due to the capability of effective carrier modulation and unique charge trapping behavior at the interfaces with atomic flatness. Here, we report a nonvolatile floating-gate flash memory based on MoTe₂/h-BN/graphene van der Waals heterostructure, which possesses increased data storage capacity per cell and versatile tunability. The decent memory behavior of the device is enabled by the carriers stored in the floating gate of graphene layer, which tunnel through the dielectric layer of h-BN from the channel layer of MoTe₂ under static-electrical field. Consequently, the developed memory device is capable to store 2 bits per cell by applying varied gate bias to implement multi-distinctive current levels. The device also exhibits remarkable erase/program current ratio of ∼10⁵ with 1 µs switch speed and stable retention with estimated ∼30% charge loss after 10 yr. Furthermore, the memory device can operate in both p- and n-type modes through contact engineering, offering wide adaptability for emerging applications in electronic technologies, such as neuromorphic computing, data-adaptive energy efficient memory, and complex digital circuits.

Logic-in-memory based on an atomically thin semiconductor

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von-Neumann architectures, brain-inspired in-memory computing uses the same basic device structure for logic operations and data storage^1–3, thus promising to reduce the energy cost of data-centric computing significantly⁴. While there is ample research focused on exploring new device architectures, the engineering of material platforms suitable for such device designs remains a challenge. Two-dimensional materials^5,6 such as semiconducting MoS2 could stand out as a promising candidate to face this obstacle thanks to their exceptional electrical and mechanical properties^7–9. Here, we explore large-area grown MoS2 as an active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFET). The conductance of our FGFETs can be precisely and continuously tuned, allowing us to use them as building blocks for reconfigurable logic circuits where logic operations can be directly performed using the memory elements. After demonstrating a programmable NOR gate, we show that this design can be simply extended to implement more complex programmable logic and functionally complete sets of functions. Our findings highlight the potential of atomically thin semiconductors for the development of next-generation low-power electronics.

Multi-level flash memory device based on stacked anisotropic ReS2-boron nitride-graphene heterostructures

Charge-trapping memory devices based on two-dimensional (2D) material heterostructures possess an atomically thin structure and excellent charge transport capability, making them promising candidates for next-generation flash memories to achieve miniaturized size, high storage capacity, fast switch speed, and low power consumption. Here, we report a nonvolatile floating-gate memory device based on an ReS₂/boron nitride/graphene heterostructure. The implemented ReS₂ memory device displays a large memory window exceeding 100 V, leading to an ultrahigh current ratio over 10⁸ between programming and erasing states. The ReS₂ memory device also exhibits an ultrafast switch speed of 1 μs. In addition, the device can endure hundreds of switching cycles and shows stable retention characteristics with ∼40% charge remaining after 10 years. More importantly, taking advantage of its anisotropic electrical properties, a single ReS₂ flake can achieve direction-sensitive multi-level data storage to enhance the data storage density. On the basis of these characteristics, the proposed ReS₂ memory device is potentially able to serve the entire memory device hierarchy, meeting the need for scalability, capacity, speed, retention, and endurance at each level.

Comprehensive Performance Quasi-Non-Volatile Memory Compatible with Large-Scale Preparation by Chemical Vapor Deposition

Two-dimensional materials with atomic thickness have become candidates for wearable electronic devices in the future. Graphene and transition metal sulfides have received extensive attention in logic computing and sensing applications due to their lower power dissipation, so that their processes have been relatively mature for large-scale preparation. However, there are a few applications of two-dimensional materials in storage, which is not in line with the development trend of integration of storage and computing. Here, a charge storage quasi-non-volatile memory with a lanthanum incorporation high-k dielectric for next-generation memory devices is proposed. Thanks to the excellent electron capture capability of LaAlO₃, the MoS₂ memory exhibits a very comprehensive information storage capability, including robust endurance and ultra-fast write speed of 1 ms approximately. It is worth mentioning that it exhibits a long-term stable charge storage capacity (refresh time is about 1000 s), which is 10⁵ times that of the dynamic random access memory (refresh time is on a milliseconds timescale) so that the unnecessary power dissipation greatly reduces caused by frequent refresh. In addition, its simple manufacturing process makes it compatible with various current two-dimensional electronic devices, which will greatly promote the integration of two-dimensional electronic computing.

Emerging Opportunities for Electrostatic Control in Atomically Thin Devices

Electrostatic control of charge carrier concentration underlies the field-effect transistor (FET), which is among the most ubiquitous devices in the modern world. As transistors and related electronic devices have been miniaturized to the nanometer scale, electrostatics have become increasingly important, leading to progressively sophisticated device geometries such as the finFET. With the advent of atomically thin materials in which dielectric screening lengths are greater than device physical dimensions, qualitatively different opportunities emerge for electrostatic control. In this Review, recent demonstrations of unconventional electrostatic modulation in atomically thin materials and devices are discussed. By combining low dielectric screening with the other characteristics of atomically thin materials such as relaxed requirements for lattice matching, quantum confinement of charge carriers, and mechanical flexibility, high degrees of electrostatic spatial inhomogeneity can be achieved, which enables a diverse range of gate-tunable properties that are useful in logic, memory, neuromorphic, and optoelectronic technologies.

Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations

A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS₂ FET can be tuned by applying an up-gate voltage pulse, which can vary the channel conductance to exhibit memory states. Through controlling the amounts of triggered molecules through either different gate voltage pulses or gate duration time, multilevel states were obtained in the molecular memory. These new molecular memory transistors exhibited an erase/program ratio of more than three orders of current magnitude and high sensitivity, of a few picoamperes, at the current level. Reproducible operation and four-level states with stable retention and endurance were achieved. We believe this prototype device has potential for use in future memory devices.

Reconfigurable Dipole-Induced Resistive Switching of MoS2 Thin Layers on Nb:SrTiO3

The controllable band gap and charge-trapping capability of MoS₂ render it suitable for use in the fabrication of various electrical devices with high-k dielectric oxides. In this study, we investigated reconfigurable resistance states in a MoS₂/Nb:SrTiO₃ heterostructure by using conductive atomic force microscopy. Low-resistance and high-resistance states were observed in all MoS₂ because of barrier height modification resulting from redistribution of charge and oxygen vacancies in the vicinity of interfaces. In a thin layer of the MoS₂ film, the carrier density was high, and layer-dependent transport properties appeared because of the charge separation in MoS₂. The hysteresis and switching voltage of the MoS₂/Nb:SrTiO₃ heterostructure could be varied by controlling the number of layers of MoS₂.

Atomic Layer Deposition of High-Quality Al2O3 Thin Films on MoS2 with Water Plasma Treatment

Atomic layer deposition (ALD) of ultrathin dielectric films on two-dimensional (2D) materials for electronic device applications remains one of the key challenges because of the lack of dangling bonds on the 2D material surface. In this work, a new technique to deposit uniform and high-quality Al₂O₃ films with thickness down to 1.5 nm on MoS₂ is introduced. By treating the surface using water plasma prior to the ALD process, hydroxyl groups are introduced to the MoS₂ surface, facilitating the chemisorption of trimethylaluminum in a conventional water-based ALD system. Raman and X-ray photoelectron spectroscopy measurements show that the water plasma treatment does not induce noticeable material degradation. The deposited Al₂O₃ films show excellent device-related electrical performance characteristics, including low interface trap density and outstanding gate controllability.

Ultrahigh Gauge Factor in Graphene/MoS2 Heterojunction Field Effect Transistor with Variable Schottky Barrier

Piezoelectricity of transition metal dichalcogenides (TMDs) under mechanical strain has been theoretically and experimentally studied. Powerful strain sensors using Schottky barrier variation in TMD/metal junctions as a result of the strain-induced lattice distortion and associated ion-charge polarization were demonstrated. However, the nearly fixed work function of metal electrodes limits the variation range of a Schottky barrier. We demonstrate a highly sensitive strain sensor using a variable Schottky barrier in a MoS₂/graphene heterostructure field effect transistor (FET). The low density of states near the Dirac point in graphene allows large modulation of the graphene Fermi level and corresponding Schottky barrier in a MoS₂/graphene junction by strain-induced polarized charges of MoS₂. Our theoretical simulations and temperature-dependent electrical measurements show that the Schottky barrier change is maximized by placing the Fermi level of the graphene at the charge neutral (Dirac) point by applying gate voltage. As a result, the maximum Schottky barrier change (ΔΦ_SB) and corresponding current change ratio under 0.17% strain reach 118 meV and 978, respectively, resulting in an ultrahigh gauge factor of 575 294, which is approximately 500 times higher than that of metal/TMD junction strain sensors (1160) and 140 times higher than the conventional strain sensors (4036). The ultrahigh sensitivity of graphene/MoS₂ heterostructure FETs can be developed for next-generation electronic and mechanical-electronic devices.

Memristive devices based on emerging two-dimensional materials beyond graphene

With the explosion of data in the information universe and the approaching of fundamental limits in silicon-based flash memories, the exploration of new device architectures and alternative materials is necessary for next-generation memory technology. Accordingly, emerging two-dimensional (2D) material-based memristive devices have attracted increasing attention due to their unique properties and great potential in flexible and wearable devices, and even neuromorphic computing systems. Herein, we provide an overview of the recent progress on memristive devices based on 2D materials beyond graphene. The device structures and choice of active materials and electrodes materials are summarized for various types of 2D material-based memristive devices. Following the discussion and classification on the device performances and mechanisms, the challenges and perspectives on future research based on 2D materials are also presented.

Controllable P- and N-Type Conversion of MoTe2 via Oxide Interfacial Layer for Logic Circuits

To realize basic electronic units such as complementary metal-oxide-semiconductor (CMOS) inverters and other logic circuits, the selective and controllable fabrication of p- and n-type transistors with a low Schottky barrier height is highly desirable. Herein, an efficient and nondestructive technique of electron-charge transfer doping by depositing a thin Al₂ O₃ layer on chemical vapor deposition (CVD)-grown 2H-MoTe₂ is utilized to tune the doping from p- to n-type. Moreover, a type-controllable MoTe₂ transistor with a low Schottky barrier height is prepared. The selectively converted n-type MoTe₂ transistor from the p-channel exhibits a maximum on-state current of 10 µA, with a higher electron mobility of 8.9 cm² V^-1 s^-1 at a drain voltage (V_ds ) of 1 V with a low Schottky barrier height of 28.4 meV. To validate the aforementioned approach, a prototype homogeneous CMOS inverter is fabricated on a CVD-grown 2H-MoTe₂ single crystal. The proposed inverter exhibits a high DC voltage gain of 9.2 with good dynamic behavior up to a modulation frequency of 1 kHz. The proposed approach may have potential for realizing future 2D transition metal dichalcogenide-based efficient and ultrafast electronic units with high-density circuit components under a low-dimensional regime.

Gate tunable giant anisotropic resistance in ultra-thin GaTe

Anisotropy in crystals arises from different lattice periodicity along different crystallographic directions, and is usually more pronounced in two dimensional (2D) materials. Indeed, in the emerging 2D materials, electrical anisotropy has been one of the recent research focuses. However, key understandings of the in-plane anisotropic resistance in low-symmetry 2D materials, as well as demonstrations of model devices taking advantage of it, have proven difficult. Here, we show that, in few-layered semiconducting GaTe, electrical conductivity anisotropy between x and y directions of the 2D crystal can be gate tuned from several fold to over 10³. This effect is further demonstrated to yield an anisotropic non-volatile memory behavior in ultra-thin GaTe, when equipped with an architecture of van der Waals floating gate. Our findings of gate-tunable giant anisotropic resistance effect pave the way for potential applications in nanoelectronics such as multifunctional directional memories in the 2D limit.

Some atomically thin crystals feature crystallographic anisotropy, but demonstrations of electrical anisotropy are scarce. Here, the authors show that the electrical conductivity of few-layered GaTe along the x and y directions can be widely gate tuned up to 10³, and demonstrate anisotropic non-volatile memory behavior.

Nonvolatile Memories Based on Graphene and Related 2D Materials

The pervasiveness of information technologies is generating an impressive amount of data, which need to be accessed very quickly. Nonvolatile memories (NVMs) are making inroads into high-capacity storage to replace hard disk drives, fuelling the expansion of the global storage memory market. As silicon-based flash memories are approaching their fundamental limit, vertical stacking of multiple memory cell layers, innovative device concepts, and novel materials are being investigated. In this context, emerging 2D materials, such as graphene, transition metal dichalcogenides, and black phosphorous, offer a host of physical and chemical properties, which could both improve existing memory technologies and enable the next generation of low-cost, flexible, and wearable storage devices. Herein, an overview of graphene and related 2D materials (GRMs) in different types of NVM cells is provided, including resistive random-access, flash, magnetic and phase-change memories. The physical and chemical mechanisms underlying the switching of GRM-based memory devices studied in the last decade are discussed. Although at this stage most of the proof-of-concept devices investigated do not compete with state-of-the-art devices, a number of promising technological advancements have emerged. Here, the most relevant material properties and device structures are analyzed, emphasizing opportunities and challenges toward the realization of practical NVM devices.

Recent Progress in the Fabrication, Properties, and Devices of Heterostructures Based on 2D Materials

With a large number of researches being conducted on two-dimensional (2D) materials, their unique properties in optics, electrics, mechanics, and magnetics have attracted increasing attention. Accordingly, the idea of combining distinct functional 2D materials into heterostructures naturally emerged that provides unprecedented platforms for exploring new physics that are not accessible in a single 2D material or 3D heterostructures. Along with the rapid development of controllable, scalable, and programmed synthesis techniques of high-quality 2D heterostructures, various heterostructure devices with extraordinary performance have been designed and fabricated, including tunneling transistors, photodetectors, and spintronic devices. In this review, we present a summary of the latest progresses in fabrications, properties, and applications of different types of 2D heterostructures, followed by the discussions on present challenges and perspectives of further investigations.

Threshold Voltage Control of Multilayered MoS2 Field-Effect Transistors via Octadecyltrichlorosilane and their Applications to Active Matrixed Quantum Dot Displays Driven by Enhancement-Mode Logic Gates

In recent past, for next-generation device opportunities such as sub-10 nm channel field-effect transistors (FETs), tunneling FETs, and high-end display backplanes, tremendous research on multilayered molybdenum disulfide (MoS₂ ) among transition metal dichalcogenides has been actively performed. However, nonavailability on a matured threshold voltage control scheme, like a substitutional doping in Si technology, has been plagued for the prosperity of 2D materials in electronics. Herein, an adjustment scheme for threshold voltage of MoS₂ FETs by using self-assembled monolayer treatment via octadecyltrichlorosilane is proposed and demonstrated to show MoS₂ FETs in an enhancement mode with preservation of electrical parameters such as field-effect mobility, subthreshold swing, and current on-off ratio. Furthermore, the mechanisms for threshold voltage adjustment are systematically studied by using atomic force microscopy, Raman, temperature-dependent electrical characterization, etc. For validation of effects of threshold voltage engineering on MoS₂ FETs, full swing inverters, comprising enhancement mode drivers and depletion mode loads are perfectly demonstrated with a maximum gain of 18.2 and a noise margin of ≈45% of 1/2 V_DD . More impressively, quantum dot light-emitting diodes, driven by enhancement mode MoS₂ FETs, stably demonstrate 120 cd m^-2 at the gate-to-source voltage of 5 V, exhibiting promising opportunities for future display application.

Doping engineering and functionalization of two-dimensional metal chalcogenides

Two-dimensional (2D) layered metal chalcogenides (MXs) have significant potential for use in flexible transistors, optoelectronics, sensing and memory devices beyond the state-of-the-art technology. To pursue ultimate performance, precisely controlled doping engineering of 2D MXs is desired for tailoring their physical and chemical properties in functional devices. In this review, we highlight the recent progress in the doping engineering of 2D MXs, covering that enabled by substitution, exterior charge transfer, intercalation and the electrostatic doping mechanism. A variety of novel doping engineering examples leading to Janus structures, defect curing effects, zero-valent intercalation and deliberately devised floating gate modulation will be discussed together with their intriguing application prospects. The choice of doping strategies and sources for functionalizing MXs will be provided to facilitate ongoing research in this field toward multifunctional applications.

Synergistic Effect of MoS2 Nanosheets and VS2 for the Hydrogen Evolution Reaction with Enhanced Humidity-Sensing Performance

As a typical transition-metal dichalcogenides, MoS₂ has been a hotspot of research in many fields. In this work, the MoS₂ nanosheets were compounded on 1T-VS₂ nanoflowers (VS₂@MoS₂) successfully by a two-step hydrothermal method for the first time, and their hydrogen evolution properties were studied mainly. The higher charge-transfer efficiency benefiting from the metallicity of VS₂ and the greater activity due to more exposed active edge sites of MoS₂ improve the hydrogen evolution reaction performance of the nanocomposite electrocatalyst. Adsorption and transport of an intermediate hydrogen atom by VS₂ also enhances the hydrogen evolution efficiency. The catalyst shows a low onset potential of 97 mV, a Tafel slope as low as 54.9 mV dec^-1, and good stability. Combining the electric conductivity of VS₂ with the physicochemical stability of MoS₂, VS₂@MoS₂ also exhibits excellent humidity properties.

Vertically Stacked and Self-Encapsulated van der Waals Heterojunction Diodes Using Two-Dimensional Layered Semiconductors

van der Waals heterojunctions using 2D semiconducting materials could overcome the defect issues included by lattice mismatch in conventional epitaxially grown heterojunctions with bulk materials and could enable a much wider palette for choice of materials and more sophisticated device design. Such 2D heterojunction devices are of great interest for important functional devices such as diodes, bipolar junction transistors, light-emitting diodes, and photodetectors. In this paper, we demonstrate a truly vertical p-n heterojunction diode built from 2D semiconductors (MoS₂ and BP) and compare its performance against conventional lateral 2D heterojunction devices (partially overlapped 2D heterostructures). Both vertical and lateral p-n heterostructure diodes exhibit a strong rectification ratio even with no gate voltage applied. More importantly, the results show that the vertical diode delivers 70 times higher current density under forward bias than a conventional lateral device design and the improved device performance can be attributed to the complete elimination of series resistance. Low-temperature measurements and TCAD simulations are used to determine the barrier height at the junctions. Moreover, the vertical device structure allows certain ambiently unstable 2D semiconductors to be fully encapsulated by the materials on top, preventing the material from degradation. This work demonstrates the potential of using the vertically stacked 2D semiconductors for future nanoelectronic and optoelectronic devices with optimal performance.

Flexible Nonvolatile Transistor Memory with Solution-Processed Transition Metal Dichalcogenides

Nonvolatile field-effect transistor (FET) memories containing transition metal dichalcogenide (TMD) nanosheets have been recently developed with great interest by utilizing some of the intriguing photoelectronic properties of TMDs. The TMD nanosheets are, however, employed as semiconducting channels in most of the memories, and only a few works address their function as floating gates. Here, a floating-gate organic-FET memory with an all-in-one floating-gate/tunneling layer of the solution-processed TMD nanosheets is demonstrated. Molybdenum disulfide (MoS₂ ) is efficiently liquid-exfoliated by amine-terminated polystyrene with a controlled amount of MoS₂ nanosheets in an all-in-one floating-gate/tunneling layer, allowing for systematic investigation of concentration-dependent charge-trapping and detrapping properties of MoS₂ nanosheets. At an optimized condition, the nonvolatile memory exhibits memory performances with an ON/OFF ratio greater than 10⁴ , a program/erase endurance cycle over 400 times, and data retention longer than 7 × 10³ s. All-in-one floating-gate/tunneling layers containing molybdenum diselenide and tungsten disulfide are also developed. Furthermore, a mechanically-flexible TMD memory on a plastic substrate shows a performance comparable with that on a hard substrate, and the memory properties are rarely altered after outer-bending events over 500 times at the bending radius of 4.0 mm.

Monolayer optical memory cells based on artificial trap-mediated charge storage and release

Monolayer transition metal dichalcogenides are considered to be promising candidates for flexible and transparent optoelectronics applications due to their direct bandgap and strong light-matter interactions. Although several monolayer-based photodetectors have been demonstrated, single-layered optical memory devices suitable for high-quality image sensing have received little attention. Here we report a concept for monolayer MoS₂ optoelectronic memory devices using artificially-structured charge trap layers through the functionalization of the monolayer/dielectric interfaces, leading to localized electronic states that serve as a basis for electrically-induced charge trapping and optically-mediated charge release. Our devices exhibit excellent photo-responsive memory characteristics with a large linear dynamic range of ∼4,700 (73.4 dB) coupled with a low OFF-state current (<4 pA), and a long storage lifetime of over 10⁴ s. In addition, the multi-level detection of up to 8 optical states is successfully demonstrated. These results represent a significant step toward the development of future monolayer optoelectronic memory devices.

Memory devices are key building blocks of image sensing circuitry. Here, the authors demonstrate a MoS₂ monolayer optoelectronic memory device based on charge trapping and subsequent optically-induced charge release, capable of 12-bit operation.

Recent Advances in Ultrathin Two-Dimensional Nanomaterials

Since the discovery of mechanically exfoliated graphene in 2004, research on ultrathin two-dimensional (2D) nanomaterials has grown exponentially in the fields of condensed matter physics, material science, chemistry, and nanotechnology. Highlighting their compelling physical, chemical, electronic, and optical properties, as well as their various potential applications, in this Review, we summarize the state-of-art progress on the ultrathin 2D nanomaterials with a particular emphasis on their recent advances. First, we introduce the unique advances on ultrathin 2D nanomaterials, followed by the description of their composition and crystal structures. The assortments of their synthetic methods are then summarized, including insights on their advantages and limitations, alongside some recommendations on suitable characterization techniques. We also discuss in detail the utilization of these ultrathin 2D nanomaterials for wide ranges of potential applications among the electronics/optoelectronics, electrocatalysis, batteries, supercapacitors, solar cells, photocatalysis, and sensing platforms. Finally, the challenges and outlooks in this promising field are featured on the basis of its current development.

High Mobility MoS2 Transistor with Low Schottky Barrier Contact by Using Atomic Thick h-BN as a Tunneling Layer

High-performance MoS₂ transistors are developed using atomic hexagonal boron nitride as a tunneling layer to reduce the Schottky barrier and achieve low contact resistance between metal and MoS₂ . Benefiting from the ultrathin tunneling layer within 0.6 nm, the Schottky barrier is significantly reduced from 158 to 31 meV with small tunneling resistance.

Size-tunable synthesis of monolayer MoS2 nanoparticles and their applications in non-volatile memory devices

We report the CVD synthesis of a monolayer of MoS₂ nanoparticles such that the nanoparticle size was controlled over the range 5-100 nm and the chemical potential of sulfur was modified, both by controlling the hydrogen flow rate during the CVD process. As the hydrogen flow rate was increased, the reaction process of sulfur changed from a "sulfiding" process to a "sulfo-reductive" process, resulting in the growth of smaller MoS₂ nanoparticles on the substrates. The size control, crystalline quality, chemical configuration, and distribution uniformity of the CVD-grown monolayer MoS₂ nanoparticles were confirmed. The growth of the MoS₂ nanoparticles at different edge states was studied using density functional theory calculations to clarify the size-tunable mechanism. A non-volatile memory device fabricated using the CVD-grown size-controlled 5 nm monolayer MoS₂ nanoparticles as a floating gate showed a good memory window of 5-8 V and an excellent retention period of a decade.

Two-bit memory and quantized storage phenomenon in conventional MOS structures with double-stacked Pt-NCs in an HfAlO matrix

Two-bit memory and quantized storage phenomenon based on double-stacked Pt-NCs in an HfAlO matrix.

Fluorinated CYTOP passivation effects on the electrical reliability of multilayer MoS₂ field-effect transistors

We demonstrated highly stable multilayer molybdenum disulfide (MoS2) field-effect transistors (FETs) with negligible hysteresis gap (ΔV(HYS) ∼ 0.15 V) via a multiple annealing scheme, followed by systematic investigation for long-term air stability with time (∼50 days) of MoS2 FETs with (or without) CYTOP encapsulation. The extracted lifetime of the device with CYTOP passivation in air was dramatically improved from 7 to 377 days, and even for the short-term bias stability, the experimental threshold voltage shift, outstandingly well-matched with the stretched exponential function, indicates that the device without passivation has approximately 25% larger the barrier distribution (ΔE(B) = k(B)T(o)) than that of a device with passivation. This work suggests that CYTOP encapsulation can be an efficient method to isolate external gas (O2 and H2O) effects on the electrical performance of FETs, especially with low-dimensional active materials like MoS2.

Transport properties of unrestricted carriers in bridge-channel MoS2 field-effect transistors

Unsuppressed carrier scattering from the underlying substrate in a layered two-dimensional material system is extensively observed, which degrades significantly the performance of devices. Beyond the material itself, understanding the intrinsic interfacial and surficial properties is an important issue for the analysis of a high-κ/MoS2 heterostructure. Here, we report on the electronic transport properties of bridge-channel MoS2 field-effect transistors fabricated by a contamination-free transfer method. After neglecting all the surrounding perturbations, it is possible to reveal the significant improvement of room-temperature mobility and subthreshold slope. A systematic study on variable-temperature transport measurements has quantified the trap density of states both in free-standing and SiO2-supported MoS2 systems. Compared to the bridge-channel MoS2 devices with an ideal interface, the unsuspended devices have a large amount of band tail states, and then the impact of their electronic states on the device performance is also discussed.

Giant magnetoresistance in zigzag MoS2 nanoribbons

Zigzag MoS₂ nanoribbons are expected to have giant magnetoresistance effect by altering the configuration from the parallel to the antiparallel spin junction.