Carbon nanotube complementary wrap-gate transistors

A DFTB study on the electronic response of encapsulated DNA nucleobases onto chiral CNTs as a sequencer

Sequencing the DNA nucleobases is essential in the diagnosis and treatment of many diseases related to human genes. In this article, the encapsulation of DNA nucleobases with some of the important synthesized chiral (7, 6), (8, 6), and (10, 8) carbon nanotubes were investigated. The structures were modeled by applying density functional theory based on tight binding method (DFTB) by considering semi-empirical basis sets. Encapsulating DNA nucleobases on the inside of CNTs caused changes in the electronic properties of the selected chiral CNTs. The results confirmed that van der Waals (vdW) interactions, π-orbitals interactions, non-bonded electron pairs, and the presence of high electronegative atoms are the key factors for these changes. The result of electronic parameters showed that among the CNTs, CNT (8, 6) is a suitable choice in sequencing guanine (G) and cytosine (C) DNA nucleobases. However, they are not able to sequence adenine (A) and thymine (T). According to the band gap energy engineering approach and absorption energy, the presence of G and C DNA nucleobases decreased the band gap energy of CNTs. Hence selected CNTs suggested as biosensor substrates for sequencing G and C DNA nucleobases.

The Schottky barrier transistor in emerging electronic devices

This paper explores how the Schottky barrier (SB) transistor is used in a variety of applications and material systems. A discussion of SB formation, current transport processes, and an overview of modeling are first considered. Three discussions follow, which detail the role of SB transistors in high performance, ubiquitous and cryogenic electronics. For high performance computing, the SB typically needs to be minimized to achieve optimal performance and we explore the methods adopted in carbon nanotube technology and two-dimensional electronics. On the contrary for ubiquitous electronics, the SB can be used advantageously in source-gated transistors and reconfigurable field-effect transistors (FETs) for sensors, neuromorphic hardware and security applications. Similarly, judicious use of an SB can be an asset for applications involving Josephson junction FETs.

Horizontal Arrays of One-Dimensional van der Waals Heterostructures as Transistor Channels

The nanotube/dielectric interface plays an essential role in achieving superb switching characteristics of carbon nanotube-based transistors for energy-efficient computation. Formation of van der Waals heterostructures with hexagonal boron nitride nanotubes could be an effective means to reduce interface state density, but the need for isolating nanotubes during the formation of coaxial outer layers has hindered the fabrication of their horizontal arrays. Here, we develop a strategy to create isolated heterostructure arrays using aligned carbon nanotubes grown on a quartz substrate as starting materials. Air-suspended arrays of carbon nanotubes are prepared by a dry transfer technique and then used as templates for the coaxial wrapping of boron nitride nanotubes. We then fabricate the transistors, where boron nitride serves as interfacial layers between carbon nanotube channels and conventional gate dielectrics, showing hysteresis-free characteristics owing to the improved interfaces. We have also gained a deeper understanding of the strain applied on inner carbon nanotubes, as well as the inhomogeneity of the outer coating, by characterizing individual heterostructures over trenches and on a substrate surface. The device fabrication and characterization presented here essentially do not require elaborate electron microscopy, thus paving the way for the practical use of one-dimensional van der Waals heterostructures for nanoelectronics.

Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays

High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been demonstrated with wafer-scale preparation of materials and have shown high performance in P-type field-effect transistors (FETs) and great potential for applications in future digital integrated circuits (ICs). However, high-performance N-type FETs (N-FETs) have not yet been implemented with A-CNTs, making development of complementary metal-oxide-semiconductor (CMOS) technology, a necessary component for modern digital ICs, impossible. In this work, we reveal the mechanism hindering the realization of A-CNT N-FETs contacted by low-work-function metals and develop corresponding solutions to promote the performance of N-FETs to that of P-type FETs (P-FETs). The fabricated scandium (Sc)-contacted A-CNT N-FET with a 100 nm gate length exhibits an on-state current (I_on) of 800 μA/μm and a peak transconductance (g_m) of 250 μS/μm, representing the highest performance of CNT-based N-FETs to date. Moreover, CMOS technology has been developed to realize N- and P-FETs with symmetric high performance based on A-CNTs. The fabricated A-CNT CMOS FETs show electron and hole mobilities of 325 and 241 cm² V^-1 s^-1, respectively, which are slightly higher than the corresponding values of Si CMOS transistors. Our scalable fabrication of A-CNT CMOS FETs with comparable electronic performance to Si CMOS will promote the application of CNT-based electronics in digital ICs.

Carbon nanotube transistors: Making electronics from molecules

Semiconducting carbon nanotubes are robust molecules with nanometer-scale diameters that can be used in field-effect transistors, from larger thin-film implementation to devices that work in conjunction with silicon electronics, and can potentially be used as a platform for high-performance digital electronics as well as radio-frequency and sensing applications. Recent progress in the materials, devices, and technologies related to carbon nanotube transistors is briefly reviewed. Emphasis is placed on the most broadly impactful advancements that have evolved from single-nanotube devices to implementations with aligned nanotubes and even nanotube thin films. There are obstacles that remain to be addressed, including material synthesis and processing control, device structure design and transport considerations, and further integration demonstrations with improved reproducibility and reliability; however, the integration of more than 10,000 devices in single functional chips has already been realized.

Nanoscale self-assembly: concepts, applications and challenges

Self-assembly offers unique possibilities for fabricating nanostructures, with different morphologies and properties, typically from vapour or liquid phase precursors. Molecular units, nanoparticles, biological molecules and other discrete elements can spontaneously organise or form via interactions at the nanoscale. Currently, nanoscale self-assembly finds applications in a wide variety of areas including carbon nanomaterials and semiconductor nanowires, semiconductor heterojunctions and superlattices, the deposition of quantum dots, drug delivery, such as mRNA-based vaccines, and modern integrated circuits and nanoelectronics, to name a few. Recent advancements in drug delivery, silicon nanoelectronics, lasers and nanotechnology in general, owing to nanoscale self-assembly, coupled with its versatility, simplicity and scalability, have highlighted its importance and potential for fabricating more complex nanostructures with advanced functionalities in the future. This review aims to provide readers with concise information about the basic concepts of nanoscale self-assembly, its applications to date, and future outlook. First, an overview of various self-assembly techniques such as vapour deposition, colloidal growth, molecular self-assembly and directed self-assembly/hybrid approaches are discussed. Applications in diverse fields involving specific examples of nanoscale self-assembly then highlight the state of the art and finally, the future outlook for nanoscale self-assembly and potential for more complex nanomaterial assemblies in the future as technological functionality increases.

Advances and Frontiers in Single-Walled Carbon Nanotube Electronics

Single-walled carbon nanotubes (SWCNTs) have been considered as one of the most promising electronic materials for the next-generation electronics in the more Moore era. Sub-10 nm SWCNT-field effect transistors (FETs) have been realized with several performances exceeding those of Si-based FETs at the same feature size. Several industrial initiatives have attempted to implement SWCNT electronics in integrated circuit (IC) chips. Here, the recent advances in SWCNT electronics are reviewed from in-depth understanding of the fundamental electronic structures, the carrier transport mechanisms, and the metal/SWCNT contact properties. In particular, the subthreshold switching properties are highlighted for low-power, energy-efficient device operations. State-of-the-art low-power SWCNT-based electronics and the key strategies to realize low-voltage and low-power operations are outlined. Finally, the essential challenges and prospects from the material preparation, device fabrication, and large-scale ICs integration for future SWCNT-based electronics are foregrounded.

Electrically Conductive Networks from Hybrids of Carbon Nanotubes and Graphene Created by Laser Radiation

A technology for the formation of electrically conductive nanostructures from single-walled carbon nanotubes (SWCNT), multi-walled carbon nanotubes (MWCNT), and their hybrids with reduced graphene oxide (rGO) on Si substrate has been developed. Under the action of single pulses of laser irradiation, nanowelding of SWCNT and MWCNT nanotubes with graphene sheets was obtained. Dependences of electromagnetic wave absorption by films of short and long nanotubes with subnanometer and nanometer diameters on wavelength are calculated. It was determined from dependences that absorption maxima of various types of nanotubes are in the wavelength region of about 266 nm. It was found that contact between nanotube and graphene was formed in time up to 400 fs. Formation of networks of SWCNT/MWCNT and their hybrids with rGO at threshold energy densities of 0.3/0.5 J/cm² is shown. With an increase in energy density above the threshold value, formation of amorphous carbon nanoinclusions on the surface of nanotubes was demonstrated. For all films, except the MWCNT film, an increase in defectiveness after laser irradiation was obtained, which is associated with appearance of C–C bonds with neighboring nanotubes or graphene sheets. CNTs played the role of bridges connecting graphene sheets. Laser-synthesized hybrid nanostructures demonstrated the highest hardness compared to pure nanotubes. Maximum hardness (52.7 GPa) was obtained for MWCNT/rGO topology. Regularity of an increase in electrical conductivity of nanostructures after laser irradiation has been established for films made of all nanomaterials. Hybrid structures of nanotubes and graphene sheets have the highest electrical conductivity compared to networks of pure nanotubes. Maximum electrical conductivity was obtained for MWCNT/rGO hybrid structure (~22.6 kS/m). Networks of nanotubes and CNT/rGO hybrids can be used to form strong electrically conductive interconnections in nanoelectronics, as well as to create components for flexible electronics and bioelectronics, including intelligent wearable devices (IWDs).

One-Dimensional van der Waals Heterojunction Diode

The synthesis of one-dimensional van der Waals heterostructures was realized recently, which offers alternative possibilities for prospective applications in electronics and optoelectronics. The even reduced dimension will enable different properties and further miniaturization beyond the capabilities of their two-dimensional counterparts. The natural doping results in p-type electrical characteristics for semiconducting single-walled carbon nanotubes and n-type for molybdenum disulfide with conventional noble metal contacts. Therefore, we demonstrate here a one-dimensional heterostructure nanotube, 11 nm wide, with the coaxial assembly of a semiconducting single-walled carbon nanotube, insulating boron nitride nanotube, and semiconducting molybdenum disulfide nanotube, which induces a radial semiconductor-insulator-semiconductor heterojunction. When opposite potential polarity was applied on a semiconducting single-walled carbon nanotube and molybdenum disulfide nanotube, respectively, the rectifying effect was materialized.

Critical challenges and advances in the carbon nanotube-metal interface for next-generation electronics

Next-generation electronics can no longer solely rely on conventional materials; miniaturization of portable electronics is pushing Si-based semiconductors and metallic conductors to their operational limits, flexible displays will make common conductive metal oxide materials obsolete, and weight reduction requirement in the aerospace industry demands scientists to seek reliable low-density conductors. Excellent electrical and mechanical properties, coupled with low density, make carbon nanotubes (CNTs) attractive candidates for future electronics. However, translating these remarkable properties into commercial macroscale applications has been disappointing. To fully realize their great potential, CNTs need to be seamlessly incorporated into metallic structures or have to synergistically work alongside them which is still challenging. Here, we review the major challenges in CNT-metal systems that impede their application in electronic devices and highlight significant breakthroughs. A few key applications that can capitalize on CNT-metal structures are also discussed. We specifically focus on the interfacial interaction and materials science aspects of CNT-metal structures.

Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices

In this paper, we report the wafer-scale fabrication of carbon nanotube field-effect transistors (CNTFETs) with the dielectrophoresis (DEP) method. Semiconducting carbon nanotubes (CNTs) were positioned as the active channel material in the fabrication of carbon nanotube field-effect transistors (CNTFETs) with dielectrophoresis (DEP). The drain-source current (I_DS) was measured as a function of the drain-source voltage (V_DS) and gate-source voltage (V_GS) from each CNTFET on the fabricated wafer. The I_DS on/off ratio was derived for each CNTFET. It was found that 87% of the fabricated CNTFETs was functional, and that among the functional CNTFETs, 30% of the CNTFETs had an I_DS on/off ratio larger than 20 while 70% of the CNTFETs had an I_DS on/off ratio lower than 20. The highest I_DS on/off ratio was about 490. The DEP-based positioning of carbon nanotubes is simple and effective, and the DEP-based device fabrication steps are compatible with Si technology processes and could lead to the wafer-scale fabrication of CNT electronic devices.

Surface passivation dictated site-selective growth of aligned carbon nanotubes

Surface defects play a significant role in the nucleation and growth of metal particles. Site-selective nucleation of metal catalyst particles, and the subsequent growth of nanostructures, could thus be accomplished by defect engineering. This paper demonstrates the switching of growth sites of vertically aligned multiwall carbon nanotubes (MW-CNTs) by manipulation of surface passivation of the substrate and discusses the possible mechanism behind this selectivity. A complementary growth pattern of CNTs is observed for pre-treatment of identically patterned SiO2/Si substrates under a reducing and non-reducing atmosphere. Variation in the number density of oxygen vacancies on the silicon dioxide surface and the presence of native oxide on the silicon face are believed to dictate the observed selectivity. The CNT architectures mimic the substrate pattern meticulously, exhibiting sharp edges, illustrating a high degree of site selectivity. The chemical state of the substrate surface and catalyst particles has been studied using Auger electron spectroscopy. Electron microscopy and Raman spectroscopy were employed to characterize the synthesized CNTs. The Hermans orientation factor was calculated to quantify the degree of alignment of the MWCNTs. Such facile control over the growth site of aligned carbon nanotubes on a substrate is a desirable aspect of synthesis for easy integration with existing silicon fabrication technology.

Energy-Efficient Tunneling Field-Effect Transistors for Low-Power Device Applications: Challenges and Opportunities

Conventional field-effect transistors (FETs) have long been considered a fundamental electronic component for a diverse range of devices. However, nanoelectronic circuits based on FETs are not energy efficient because they require a large supply voltage for switching applications. To reduce the supply voltage in standard FETs, which is hampered by the 60 mV/decade limit established by the subthreshold swing (SS), a new class of FETs have been designed, tunnel FETs (TFETs). A TFET utilizes charge-carrier transportation in device channels using quantum mechanical based band-to-band tunneling despite of conventional thermal injection. The TFETs fabricated with thin semiconducting film or nanowires can attain a 100-fold power drop compared to complementary metal-oxide-semiconductor (CMOS) transistors. As a result, the use of TFETs and CMOS technology together could ameliorate integrated circuits for low-power devices. The discovery of two-dimensional (2D) materials with a diverse range of electronic properties has also opened new gateways for condensed matter physics, nanotechnology, and material science, thus potentially improving TFET-based devices in terms of device design and performance. In this review, state-of-art TFET devices exhibiting different semiconducting channels and geometries are comprehensively reviewed followed by a brief discussion of the challenges that remain for the development of high-performance devices. Lastly, future prospects are presented for the improvement of device design and the working efficiency of TFETs.

Noise and charge discreteness as ultimate limit for the THz operation of ultra-small electronic devices

To manufacture faster electron devices, the industry has entered into the nanoscale dimensions and Terahertz (THz) working frequencies. The discrete nature of the few electrons present simultaneously in the active region of ultra-small devices generate unavoidable fluctuations of the current at THz frequencies. The consequences of this noise remain unnoticed in the scientific community because its accurate understanding requires dealing with consecutive multi-time quantum measurements. Here, a modeling of the quantum measurement of the current at THz frequencies is introduced in terms of quantum (Bohmian) trajectories. With this new understanding, we develop an analytic model for THz noise as a function of the electron transit time and the sampling integration time, which finally determine the maximum device working frequency for digital applications. The model is confirmed by either semi-classical or full- quantum time-dependent Monte Carlo simulations. All these results show that intrinsic THz noise increases unlimitedly when the volume of the active region decreases. All attempts to minimize the low signal-to-noise ratio of these ultra-small devices to get effective THz working frequencies are incompatible with the basic elements of the scaling strategy. One can develop THz electron devices, but they cannot have ultra-small dimensions. Or, one can fabricate ultra-small electron devices, but they cannot be used for THz working frequencies.

Channel Length-Dependent Operation of Ambipolar Schottky-Barrier Transistors on a Single Si Nanowire

For use in flexible, printable, wearable electronics, Schottky-barrier field-effect transistors (SB-FETs) with various channel materials including low-dimensional nanomaterials have been considered so far due to their comparatively simple and cost-effective integration scheme free of junction and channel dopants. However, the electric conduction mechanism and the scaling properties underlying their performance differ significantly from those of conventional metal-oxide-semiconductor (MOS) field-effect transistors. Indeed, an understanding of channel length scaling and drain bias impact has not been elucidated sufficiently. Here, multiple ambipolar SB-FETs with different channel lengths have been fabricated on a single silicon nanowire ensuring a constant nanowire diameter. Their length scaling behavior is analyzed through drain current and transconductance contour maps, each depending on the drain and gate bias. The reduced gate control and extended drain field effect on Schottky junctions were observed in short channels. Activation energy measurements showed lower sensitive behavior of the Schottky barrier to gate bias in the short-channel device and confirmed the thinning of Schottky barrier width for electrons at the source interface with drain bias.

Nanoscale Patterning of Carbon Nanotubes: Techniques, Applications, and Future

Carbon nanotube (CNT) devices and electronics are achieving maturity and directly competing or surpassing devices that use conventional materials. CNTs have demonstrated ballistic conduction, minimal scaling effects, high current capacity, low power requirements, and excellent optical/photonic properties; making them the ideal candidate for a new material to replace conventional materials in next-generation electronic and photonic systems. CNTs also demonstrate high stability and flexibility, allowing them to be used in flexible, printable, and/or biocompatible electronics. However, a major challenge to fully commercialize these devices is the scalable placement of CNTs into desired micro/nanopatterns and architectures to translate the superior properties of CNTs into macroscale devices. Precise and high throughput patterning becomes increasingly difficult at nanoscale resolution, but it is essential to fully realize the benefits of CNTs. The relatively long, high aspect ratio structures of CNTs must be preserved to maintain their functionalities, consequently making them more difficult to pattern than conventional materials like metals and polymers. This review comprehensively explores the recent development of innovative CNT patterning techniques with nanoscale lateral resolution. Each technique is critically analyzed and applications for the nanoscale-resolution approaches are demonstrated. Promising techniques and the challenges ahead for future devices and applications are discussed.

Conformal High-K Dielectric Coating of Suspended Single-Walled Carbon Nanotubes by Atomic Layer Deposition

As one of the highest mobility semiconductor materials, carbon nanotubes (CNTs) have been extensively studied for use in field effect transistors (FETs). To fabricate surround-gate FETs- which offer the best switching performance-deposition of conformal, weakly-interacting dielectric layers is necessary. This is challenging due to the chemically inert surface of CNTs and a lack of nucleation sites-especially for defect-free CNTs. As a result, a technique that enables integration of uniform high-k dielectrics, while preserving the CNT's exceptional properties is required. In this work, we show a method that enables conformal atomic layer deposition (ALD) of high-k dielectrics on defect-free CNTs. By depositing a thin Ti metal film, followed by oxidation to TiO₂ under ambient conditions, a nucleation layer is formed for subsequent ALD deposition of Al₂O₃. The technique is easy to implement and is VLSI-compatible. We show that the ALD coatings are uniform, continuous and conformal, and Raman spectroscopy reveals that the technique does not induce defects in the CNT. The resulting bilayer TiO₂/Al₂O₃ thin-film shows an improved dielectric constant of 21.7 and an equivalent oxide thickness of 2.7 nm. The electrical properties of back-gated and top-gated devices fabricated using this method are presented.

Nanoscale FET-Based Transduction toward Sensitive Extended-Gate Biosensors

Owing to their simple and low-cost architecture, extended-gate biosensors based on the combination of a disposable sensing part and a reusable transducer have been widely utilized for the label-free electrical detection of chemical and biological species. Previous studies have demonstrated that sensitive and selective detection of ions and biomolecules can be achieved by controlled modification of the sensing part with an ion-selective membrane and receptors of interest. However, no systematic studies have been performed on the impact of the transducer on sensing performance. In this paper, we introduce the concept of a nanoscale field-effect transistor (FET) as a reusable and sensitive transducer for extended-gate biosensors. The capacitive effect from the external sensing part can degrade the sensing performance, but the nanoscale FET can reduce this effect. The nanoscale FET with a gate-all-around (GAA) structure exhibits a higher pH sensitivity than a commercially available FET, which is widely used in conventional extended-gate biosensors. A sensitivity reduction is observed for the commercial FET, whereas the pH sensitivity is insensitive to the area of the sensing region in the nanoscale FET, thus allowing the scaling of the detection area. Our analysis based on a capacitive model suggests that the high pH sensitivity in the compact sensing area originates from the small input capacitance of the nanoscale FET transducer. Moreover, a decrease in the nanowire width of the GAA FET leads to an improvement in the pH sensitivity. The extended-gate approach with the nanoscale FET-based transduction can pave the way for a highly sensitive analysis of chemical and biological species with a small sample volume.

Tiny nano-scale junction built on B/N doped single carbon nanotube

The characteristic sizes of carbon nanotube (CNT)-based devices are constantly being reduced. However, this continuing miniaturization is still facing many problems and requires innovative ideas and structures. By regular doping of boron and nitrogen atoms in a semiconducting single-wall carbon nanotube (SWCNT), we have constructed a nano-scale junction with rectifying characteristics. The I-V curve of our junction resembles the I-V curve of an ideal diode with a p-n junction. This junction channel is about 0.6 nm wide and 3.4 nm long, and the footprint is 5.1 nm long. Under a 0.5 V bias, the junction has a leakage current of -8.8 × 10^-3 μA, a rectifying ratio I_on/I_off of 0.716 × 10³, and a current density of 10.52 mA μm^-1. Our study also shows how different dopant distributions influence the I-V curve. Such a regular nano-scale doping method is effective and important, compared with the traditional random doping method.

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm²) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10⁸, 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

Scaling down contact length in complementary carbon nanotube field-effect transistors

We performed an experimental investigation on contact length (L_c) scaling of carbon nanotube (CNT) complementary field-effect transistors (FETs). Contact resistances of Sc-contacted (for n-type) and Pd-contacted (for p-type) CNT FETs are respectively retrieved based on the experimental data through the transfer length method (TLM). The performance of L_c scaling of Sc/CNT is proved to be comparable to that of the Pd/CNT contact with L_c larger than approximately 40 nm, but it degrades sharply when further scaling down L_c mainly owing to the surface oxidation of the Sc film. After decoupling the effect of oxide thickness, the intrinsic contact scaling behavior of Sc-contacted CNT FETs is found to be as good as that of the Pd-contacted ones, which can further satisfy the requirement of developing complementary CNT FET technology scaled down to the 14 nm node.

Endeavor of Iontronics: From Fundamentals to Applications of Ion-Controlled Electronics

Iontronics is a newly emerging interdisciplinary concept which bridges electronics and ionics, covering electrochemistry, solid-state physics, electronic engineering, and biological sciences. The recent developments of electronic devices are highlighted, based on electric double layers formed at the interface between ionic conductors (but electronically insulators) and various electronic conductors including organics and inorganics (oxides, chalcogenide, and carbon-based materials). Particular attention is devoted to electric-double-layer transistors (EDLTs), which are producing a significant impact, particularly in electrical control of phase transitions, including superconductivity, which has been difficult or impossible in conventional all-solid-state electronic devices. Besides that, the current state of the art and the future challenges of iontronics are also reviewed for many applications, including flexible electronics, healthcare-related devices, and energy harvesting.

Carbon nanotube transistors scaled to a 40-nanometer footprint

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density—above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays.

Hysteresis-Free Carbon Nanotube Field-Effect Transistors

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

Horizontally aligned carbon nanotube arrays: growth mechanism, controlled synthesis, characterization, properties and applications

This review summarizes the growth mechanism, controlled synthesis, characterization, properties and applications of horizontally aligned carbon nanotube arrays.

Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor

Three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated on a large scale 8 in. silicon wafer. The fabricated 3-D CNT-FETs take advantage of the 3-D geometry and exhibit enhanced electrostatic gate controllability and superior charge transport. A trigated structure surrounding the randomly networked single-walled CNT channel was formed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm. Additionally, highly sensitive controllability of the threshold voltage (V_TH) was achieved using a thin back gate oxide in the same silicon frame to control power consumption and enhance performance. Our results are expected to broaden the design margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentially provide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerging low-dimensional materials other than CNTs.

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G 0 = 4e (2)/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G 0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm(-1), fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G 0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm(-1), which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm(-1) and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies.

Highly Efficient and Scalable Separation of Semiconducting Carbon Nanotubes via Weak Field Centrifugation

The identification of scalable processes that transfer random mixtures of single-walled carbon nanotubes (SWCNTs) into fractions featuring a high content of semiconducting species is crucial for future application of SWCNTs in high-performance electronics. Herein we demonstrate a highly efficient and simple separation method that relies on selective interactions between tailor-made amphiphilic polymers and semiconducting SWCNTs in the presence of low viscosity separation media. High purity individualized semiconducting SWCNTs or even self-organized semiconducting sheets are separated from an as-produced SWCNT dispersion via a single weak field centrifugation run. Absorption and Raman spectroscopy are applied to verify the high purity of the obtained SWCNTs. Furthermore SWCNT - network field-effect transistors were fabricated, which exhibit high ON/OFF ratios (10⁵) and field-effect mobilities (17 cm²/Vs). In addition to demonstrating the feasibility of high purity separation by a novel low complexity process, our method can be readily transferred to large scale production.

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

On the Control of the Fixed Charge Densities in Al2O3-Based Silicon Surface Passivation Schemes

A controlled field-effect passivation by a well-defined density of fixed charges is crucial for modern solar cell surface passivation schemes. Al2O3 nanolayers grown by atomic layer deposition contain negative fixed charges. Electrical measurements on slant-etched layers reveal that these charges are located within a 1 nm distance to the interface with the Si substrate. When inserting additional interface layers, the fixed charge density can be continuously adjusted from 3.5 × 10(12) cm(-2) (negative polarity) to 0.0 and up to 4.0 × 10(12) cm(-2) (positive polarity). A HfO2 interface layer of one or more monolayers reduces the negative fixed charges in Al2O3 to zero. The role of HfO2 is described as an inert spacer controlling the distance between Al2O3 and the Si substrate. It is suggested that this spacer alters the nonstoichiometric initial Al2O3 growth regime, which is responsible for the charge formation. On the basis of this charge-free HfO2/Al2O3 stack, negative or positive fixed charges can be formed by introducing additional thin Al2O3 or SiO2 layers between the Si substrate and this HfO2/Al2O3 capping layer. All stacks provide very good passivation of the silicon surface. The measured effective carrier lifetimes are between 1 and 30 ms. This charge control in Al2O3 nanolayers allows the construction of zero-fixed-charge passivation layers as well as layers with tailored fixed charge densities for future solar cell concepts and other field-effect based devices.

Recent Progress in Obtaining Semiconducting Single-Walled Carbon Nanotubes for Transistor Applications

High purity semiconducting single-walled carbon nanotubes (s-SWCNTs) with a narrow diameter distribution are required for high-performance transistors. Achieving this goal is extremely challenging because the as-grown material contains mixtures of s-SWCNTs and metallic- (m-) SWCNTs with wide diameter distributions, typically inadequate for integrated circuits. Since 2000, numerous ex situ methods have been proposed to improve the purity of the s-SWCNTs. The majority of these techniques fail to maintain the quality and integrity of the s-SWCNTs with a few notable exceptions. Here, the progress in realizing high purity s-SWCNTs in as-grown and post-processed materials is highlighted. A comparison of transistor parameters (such as on/off ratio and field-effect mobility) obtained from test structures establishes the effectiveness of various methods and suggests opportunities for future improvements.

High-Performance Wrap-Gated InGaAs Nanowire Field-Effect Transistors with Sputtered Dielectrics

Although wrap-gated nanowire field-effect-transistors (NWFETs) have been explored as an ideal electronic device geometry for low-power and high-frequency applications, further performance enhancement and practical implementation are still suffering from electron scattering on nanowire surface/interface traps between the nanowire channel and gate dielectric as well as the complicated device fabrication scheme. Here, we report the development of high-performance wrap-gated InGaAs NWFETs using conventional sputtered Al₂O₃ layers as gate dielectrics, instead of the typically employed atomic layer deposited counterparts. Importantly, the surface chemical passivation of NW channels performed right before the dielectric deposition is found to significantly alleviate plasma induced defect traps on the NW channel. Utilizing this passivation, the wrap-gated device exhibits superior electrical performances: a high I_ON/I_OFF ratio of ~2 × 10⁶, an extremely low sub-threshold slope of 80 mV/decade and a peak field-effect electron mobility of ~1600 cm²/(Vs) at V_DS = 0.1 V at room temperature, in which these values are even better than the ones of state-of-the-art NWFETs reported so far. By combining sputtering and pre-deposition chemical passivation to achieve high-quality gate dielectrics for wrap-gated NWFETs, the superior gate coupling and electrical performances have been achieved, confirming the effectiveness of our hybrid approach for future advanced electronic devices.

Carbon Nanotube Synaptic Transistor Network for Pattern Recognition

Inspired by the human brain, a neuromorphic system combining complementary metal-oxide semiconductor (CMOS) and adjustable synaptic devices may offer new computing paradigms by enabling massive neural-network parallelism. In particular, synaptic devices, which are capable of emulating the functions of biological synapses, are used as the essential building blocks for an information storage and processing system. However, previous synaptic devices based on two-terminal resistive devices remain challenging because of their variability and specific physical mechanisms of resistance change, which lead to a bottleneck in the implementation of a high-density synaptic device network. Here we report that a three-terminal synaptic transistor based on carbon nanotubes can provide reliable synaptic functions that encode relative timing and regulate weight change. In addition, using system-level simulations, the developed synaptic transistor network associated with CMOS circuits can perform unsupervised learning for pattern recognition using a simplified spike-timing-dependent plasticity scheme.

Solution-processed carbon nanotube thin-film complementary static random access memory

Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

End-bonded contacts for carbon nanotube transistors with low, size-independent resistance

Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube (SWNT) transistor technology with an end-bonded contact scheme that leads to size-independent contact resistance to overcome the scaling limits of conventional side-bonded or planar contact schemes. A high-performance SWNT transistor was fabricated with a sub–10-nanometer contact length, showing a device resistance below 36 kilohms and on-current above 15 microampere per tube. The p-type end-bonded contact, formed through the reaction of molybdenum with the SWNT to form carbide, also exhibited no Schottky barrier. This strategy promises high-performance SWNT transistors, enabling future ultimately scaled device technologies.

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices.

Wetting transition for carbon nanotube arrays under metal contacts

Structural arrays with nanoscale spacing arise in many device concepts. Carbon nanotube transistors are an extreme example, where a practical technology will require arrays of parallel nanotubes with spacing of order 10 nm or less. We show that with decreasing pitch there is a first-order transition, from a robust structure in which the metal wets the substrate between tubes, to a poorly wetting structure in which the metal rides atop the nanotube array without touching the substrate. The latter is analogous to the superhydrophobic "lotus leaf effect." There is a sharp minimum in the delamination energy of metal contacts at the transition pitch. We discuss implications for contact resistance and possible mitigation strategies.

Origins and characteristics of the threshold voltage variability of quasiballistic single-walled carbon nanotube field-effect transistors

Ultrascaled transistors based on single-walled carbon nanotubes are identified as one of the top candidates for future microprocessor chips as they provide significantly better device performance and scaling properties than conventional silicon technologies. From the perspective of the chip performance, the device variability is as important as the device performance for practical applications. This paper presents a systematic investigation on the origins and characteristics of the threshold voltage (VT) variability of scaled quasiballistic nanotube transistors. Analysis of experimental results from variable-temperature measurement as well as gate oxide thickness scaling studies shows that the random variation from fixed charges present on the oxide surface close to nanotubes dominates the VT variability of nanotube transistors. The VT variability of single-tube transistors has a figure of merit that is quantitatively comparable with that of current silicon devices; and it could be reduced with the adoption of improved device passivation schemes, which might be necessary for practical devices incorporating multiple nanotubes, whose area normalized VT variability becomes worse due to the synergic effects from the limited surface coverage of nanotubes and the nonlinearity of the device off-state leakage current, as predicted by the Monte Carlo simulation.

Non-destructive functionalisation for atomic layer deposition of metal oxides on carbon nanotubes: effect of linking agents and defects

The hybridisation of metal oxides and nanocarbons has created a promising new class of functional materials for environmental and sustainable energy applications. The performance of such hybrids can be further improved by rationally designing interfaces and morphologies. Atomic layer deposition (ALD) is among the most powerful techniques for the controlled deposition of inorganic compounds, due to its ability to form conformal coatings on porous substrates at low temperatures with high surface sensitivity and atomic control of film thickness. The hydrophobic nature of the nanocarbon surface has so far limited the applicability of ALD on CNTs. Herein we investigate the role of structural defects in CNTs, both intrinsic and induced by acid treatment, on coverage, uniformity and crystallinity of ZnO coatings. Furthermore, we demonstrate the potential of small aromatic molecules, including benzyl alcohol (BA), naphthalene carboxylic acid (NA) and pyrene carboxylic acid (PCA), as active nucleation sites and linking agents. Importantly, only PCA exhibits sufficiently strong interactions with the pristine CNT surface to withstand desorption under reaction conditions. Thus, PCA enables a versatile and non-destructive alternative route for the deposition of highly uniform metal oxide coatings onto pristine CNTs via ALD over a wide temperature range and without the typical surface corrosion induced by covalent functionalisation. Importantly, preliminary tests demonstrated that the improved morphology obtained with PCA has indeed considerably increased the hybrid's photocatalytic activity towards hydrogen evolution via sacrificial water splitting. The concept demonstrated in this work is transferable to a wide range of other inorganic compounds including metal oxides, metal (oxy)nitrides and metal chalcogenides on a variety of nanocarbons.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Highly uniform and stable n-type carbon nanotube transistors by using positively charged silicon nitride thin films

Air-stable n-doping of carbon nanotubes is presented by utilizing SiN(x) thin films deposited by plasma-enhanced chemical vapor deposition. The fixed positive charges in SiN(x), arising from (+)Si ≡ N3 dangling bonds induce strong field-effect doping of underlying nanotubes. Specifically, an electron doping density of ∼ 10(20) cm(-3) is estimated from capacitance voltage measurements of the fixed charge within the SiN(x). This high doping concentration results in thinning of the Schottky barrier widths at the nanotube/metal contacts, thus allowing for efficient injection of electrons by tunnelling. As a proof-of-concept, n-type thin-film transistors using random networks of semiconductor-enriched nanotubes are presented with an electron mobility of ∼ 10 cm(2)/V s, which is comparable to the hole mobility of as-made p-type devices. The devices are highly stable without any noticeable change in the electrical properties upon exposure to ambient air for 30 days. Furthermore, the devices exhibit high uniformity over large areas, which is an important requirement for use in practical applications. The work presents a robust approach for physicochemical doping of carbon nanotubes by relying on field-effect rather than a charge transfer mechanism.

Nanospot welding of carbon nanotubes using near-field enhancement effect of AFM probe irradiated by optical fiber probe laser

The carbon nanotubes interconnection can be achieved by the new nanospot welding method with the near-field enhancement effect of the metallic AFM probe tip irradiated by optical fiber probe laser.

Exploration of yttria films as gate dielectrics in sub-50 nm carbon nanotube field-effect transistors

Thin yttria films were investigated for use as gate dielectrics in carbon nanotube field-effect transistors (CNTFETs) with the gate length scaled down to sub-50 nm size. The yttria film provided an omega-shaped gate dielectric with a low interface trap density, a low average sub-threshold swing of 74 mV per decade for both long and short CNTFETs, and a small drain-induced barrier lowering. It was also shown that the performance of CNTFETs increases with decreasing temperature, with an excellent sub-threshold swing of 22 mV per decade at liquid nitrogen temperatures. A method was developed to retrieve the interface trap density in CNTFETs and a low interface trap density of 5.2 × 10(6) cm(-1) was achieved, indicating the high electric quality of the yttria films.

Toward high-performance digital logic technology with carbon nanotubes

The slow-down in traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling (Moore's law) has created an opportunity for a disruptive innovation to bring the semiconductor industry into a postsilicon era. Due to their ultrathin body and ballistic transport, carbon nanotubes (CNTs) have the intrinsic transport and scaling properties to usher in this new era. The remaining challenges are largely materials-related and include obtaining purity levels suitable for logic technology, placement of CNTs at very tight (∼5 nm) pitch to allow for density scaling and source/drain contact scaling. This review examines the potential performance advantages of a CNT-based computing technology, outlines the remaining challenges, and describes the recent progress on these fronts. Although overcoming these issues will be challenging and will require a large, sustained effort from both industry and academia, the recent progress in the field is a cause for optimism that these materials can have an impact on future technologies.

Single electron charge sensitivity of liquid-gated carbon nanotube transistors

Random telegraph signals corresponding to activated charge traps were observed with liquid-gated CNT FETs. The high signal-to-noise ratio that we observe demonstrates that single electron charge sensing is possible with CNT FETs in liquids at room temperature. We have characterized the gate-voltage dependence of the random telegraph signals and compared to theoretical predictions. The gate-voltage dependence clearly identifies the sign of the activated trapped charge.