A compute-in-memory chip based on resistive random-access memory

The 3D Monolithically Integrated Hardware Based Neural System with Enhanced Memory Window of the Volatile and Non-Volatile Devices

3D neuromorphic hardware system is first demonstrated in neuromorphic application as on-chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non-volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware-based neural system, considering the possibility of device degradation in both volatile and non-volatile memory devices demonstrated by the hardware neural system.

High-performance flexible resistive random-access memory based on SnS2 quantum dots with a charge trapping/de-trapping effect

The application of resistive random-access memory (RRAM) in storage and neuromorphic computing has attracted widespread attention. Benefitting from the quantum effect, transition metal dichalcogenides (TMD) quantum dots (QDs) exhibit distinctive optical and electronic properties, which make them promising candidates for emerging RRAM. Here, we show a high-performance forming-free flexible RRAM based on high-quality tin disulfide (SnS2) QDs prepared by a facile liquid phase method. The RRAM device demonstrates high flexibility with a large on/off ratio of ∼106 and a long retention time of over 3 × 104 s. The excellent switching behavior of the memristor is elucidated by a charge trapping/de-trapping mechanism where the SnS2 QDs act as charge trapping centers. This study is of significance for the understanding and development of TMD QD-based flexible memristors.

Synergistically Modulating Conductive Filaments in Ion-Based Memristors for Enhanced Analog In-Memory Computing

Memristors offer a promising solution to address the performance and energy challenges faced by conventional von Neumann computer systems. Yet, stochastic ion migration in conductive filament often leads to an undesired performance tradeoff between memory window, retention, and endurance. Herein, a robust memristor based on oxygen-rich SnO2 nanoflowers switching medium, enabled by seed-mediated wet chemistry, to overcome the ion migration issue for enhanced analog in-memory computing is reported. Notably, the interplay between the oxygen vacancy (Vo) and Ag ions (Ag+) in the Ag/SnO2/p++-Si memristor can efficiently modulate the formation and abruption of conductive filaments, thereby resulting in a high on/off ratio (>106), long memory retention (10-year extrapolation), and low switching variability (SV = 6.85%). Multiple synaptic functions, such as paired-pulse facilitation, long-term potentiation/depression, and spike-time dependent plasticity, are demonstrated. Finally, facilitated by the symmetric analog weight updating and multiple conductance states, a high image recognition accuracy of ≥ 91.39% is achieved, substantiating its feasibility for analog in-memory computing. This study highlights the significance of synergistically modulating conductive filaments in optimizing performance trade-offs, balancing memory window, retention, and endurance, which demonstrates techniques for regulating ion migration, rendering them a promising approach for enabling cutting-edge neuromorphic applications.

Modulation of polyaniline memristive device switching voltage by nucleotide-free analogue of vitamin B12

Memristive devices offer essential properties to become a part of the next-generation computing systems based on neuromorphic principles. Organic memristive devices exhibit a unique set of properties which makes them an indispensable choice for specific applications, such as interfacing with biological systems. While the switching rate of organic devices can be easily adjusted over a wide range through various methods, controlling the switching potential is often more challenging, as this parameter is intricately tied to the materials used. Given the limited options in the selection conductive polymers and the complexity of polymer chemical engineering, the most straightforward and accessible approach to modulate switching potentials is by introducing specific molecules into the electrolyte solution. In our study, we show polyaniline (PANI)-based device switching potential control by adding nucleotide-free analogue of vitamin B12, aquacyanocobinamide, to the electrolyte solution. The employed concentrations of this molecule, ranging from 0.2 to 2 mM, enabled organic memristive devices to achieve switching potential decrease for up to 100 mV, thus providing a way to control device properties. This effect is attributed to strong aromatic interactions between PANI phenyl groups and corrin macrocycle of the aquacyanocobinamide molecule, which was supported by ultraviolet-visible spectra analysis.

Domain wall magnetic tunnel junction-based artificial synapses and neurons for all-spin neuromorphic hardware

We report a breakthrough in the hardware implementation of energy-efficient all-spin synapse and neuron devices for highly scalable integrated neuromorphic circuits. Our work demonstrates the successful execution of all-spin synapse and activation function generator using domain wall-magnetic tunnel junctions. By harnessing the synergistic effects of spin-orbit torque and interfacial Dzyaloshinskii-Moriya interaction in selectively etched spin-orbit coupling layers, we achieve a programmable multi-state synaptic device with high reliability. Our first-principles calculations confirm that the reduced atomic distance between 5d and 3d atoms enhances Dzyaloshinskii-Moriya interaction, leading to stable domain wall pinning. Our experimental results, supported by visualizing energy landscapes and theoretical simulations, validate the proposed mechanism. Furthermore, we demonstrate a spin-neuron with a sigmoidal activation function, enabling high operation frequency up to 20 MHz and low energy consumption of 508 fJ/operation. A neuron circuit design with a compact sigmoidal cell area and low power consumption is also presented, along with corroborated experimental implementation. Our findings highlight the great potential of domain wall-magnetic tunnel junctions in the development of all-spin neuromorphic computing hardware, offering exciting possibilities for energy-efficient and scalable neural network architectures.

Organic Synaptic Transistors with Environmentally Friendly Core/Shell Quantum Dots for Wavelength-Selective Memory and Neuromorphic Functions

Organic transistors based on organic semiconductors together with quantum dots (QDs) are attracting more and more interest because both materials have excellent optoelectronic properties and solution processability. Electronics based on nontoxic QDs are highly desired considering the potential health risks but are limited by elevated surface defects, inadequate stability, and diminished luminescent efficiency. Herein, organic synaptic transistors based on environmentally friendly ZnSe/ZnS core/shell QDs with passivating surface defects are developed, exhibiting optically programmable and electrically erasable characteristics. The synaptic transistors feature linear multibit storage capability and wavelength-selective memory function with a retention time above 6000 s. Various neuromorphic applications, including memory enhancement, optical communication, and memory consolidation behaviors, are simulated. Utilizing an established neuromorphic model, accuracies of 92% and 91% are achieved in pattern recognition and complicated electrocardiogram signal processing, respectively. This research highlights the potential of environmentally friendly QDs in neuromorphic applications and health monitoring.

Optimisation Challenge for a Superconducting Adiabatic Neural Network That Implements XOR and OR Boolean Functions

In this article, we consider designs of simple analog artificial neural networks based on adiabatic Josephson cells with a sigmoid activation function. A new approach based on the gradient descent method is developed to adjust the circuit parameters, allowing efficient signal transmission between the network layers. The proposed solution is demonstrated on the example of a system that implements XOR and OR logical operations.

Restricted Boltzmann Machines Implemented by Spin-Orbit Torque Magnetic Tunnel Junctions

Artificial intelligence has surged forward with the advent of generative models, which rely heavily on stochastic computing architectures enhanced by true random number generators with adjustable sampling probabilities. In this study, we develop spin-orbit torque magnetic tunnel junctions (SOT-MTJs), investigating their sigmoid-style switching probability as a function of the driving voltage. This feature proves to be ideally suited for stochastic computing algorithms such as the restricted Boltzmann machines (RBM) prevalent in pretraining processes. We exploit SOT-MTJs as both stochastic samplers and network nodes for RBMs, enabling the implementation of RBM-based neural networks to achieve recognition tasks for both handwritten and spoken digits. Moreover, we further harness the weights derived from the preceding image and speech training processes to facilitate cross-modal learning from speech to image generation. Our results clearly demonstrate that these SOT-MTJs are promising candidates for the development of hardware accelerators tailored for Boltzmann neural networks and other stochastic computing architectures.

Reliability effects of lateral filament confinement by nano-scaling the oxide in memristive devices

Write-variability and resistance instability are major reliability concerns impeding implementation of oxide-based memristive devices in neuromorphic systems. The root cause of the reliability issues is the stochastic nature of conductive filament formation and dissolution, whose impact is particularly critical in the high resistive state (HRS). Optimizing the filament stability requires mitigating diffusive processes within the oxide, but these are unaffected by conventional electrode scaling. Here we propose a device design that laterally confines the switching oxide volume and thus the filament to 10 nm, which yields reliability improvements in our measurements and simulations. We demonstrate a 50% decrease in HRS write-variability for an oxide nano-fin device in our full factorial analysis of modulated current-voltage sweeps. Furthermore, we use ionic noise measurements to quantify the HRS filament stability against diffusive processes. The laterally confined filaments exhibit a change in the signal-to-noise ratio distribution with a shift to higher values. Our complementing kinetic Monte Carlo simulation of oxygen vacancy (re-)distribution for confined filaments shows improved noise behavior and elucidates the underlying physical mechanisms. While lateral oxide volume scaling down to filament sizes is challenging, our efforts motivate further examination and awareness of filament confinement effects in regards to reliability.

Unraveling the origins of the coexisting localized-interfacial mechanism in oxide-based memristors in CMOS-integrated synaptic device implementations

The forefront of neuromorphic research strives to develop devices with specific properties, i.e., linear and symmetrical conductance changes under external stimuli. This is paramount for neural network accuracy when emulating a biological synapse. A parallel exploration of resistive memory as a replacement for conventional computing memory ensues. In search of a holistic solution, the proposed memristive device in this work is uniquely poised to address this elusive gap as a unified memory solution. Opposite biasing operations are leveraged to achieve stable abrupt and gradual switching characteristics within a single device, addressing the demands for lower latency and energy consumption for binary switching applications, and graduality for neuromorphic computing applications. We evaluated the underlying principles of both switching modes, attributing the anomalous gradual switching to the modulation of oxygen-deficient layers formed between the active electrode and oxide switching layer. The memristive cell (1R) was integrated with 40 nm transistor technology (1T) to form a 1T-1R memory cell, demonstrating a switching speed of 50 ns with a pulse amplitude of ±2.5 V in its forward-biased mode. Applying pulse trains of 20 ns to 490 ns in the reverse-biased mode exhibited synaptic weight properties, obtaining a nonlinearity (NL) factor of <0.5 for both potentiation and depression. The devices in both modes also demonstrated an endurance of >106 cycles, and their conductance states were also stable under temperature stress at 85 °C for 104 s. With the duality of the two switching modes, our device can be used for both memory and synaptic weight-storing applications.

Multi-level, forming and filament free, bulk switching trilayer RRAM for neuromorphic computing at the edge

CMOS-RRAM integration holds great promise for low energy and high throughput neuromorphic computing. However, most RRAM technologies relying on filamentary switching suffer from variations and noise, leading to computational accuracy loss, increased energy consumption, and overhead by expensive program and verify schemes. We developed a filament-free, bulk switching RRAM technology to address these challenges. We systematically engineered a trilayer metal-oxide stack and investigated the switching characteristics of RRAM with varying thicknesses and oxygen vacancy distributions to achieve reliable bulk switching without any filament formation. We demonstrated bulk switching at megaohm regime with high current nonlinearity, up to 100 levels without compliance current. We developed a neuromorphic compute-in-memory platform and showcased edge computing by implementing a spiking neural network for an autonomous navigation/racing task. Our work addresses challenges posed by existing RRAM technologies and paves the way for neuromorphic computing at the edge under strict size, weight, and power constraints.

Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) andHf 0.5 Zr 0.5 O 2 (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods.

DenRAM: neuromorphic dendritic architecture with RRAM for efficient temporal processing with delays

An increasing number of studies are highlighting the importance of spatial dendritic branching in pyramidal neurons in the neocortex for supporting non-linear computation through localized synaptic integration. In particular, dendritic branches play a key role in temporal signal processing and feature detection. This is accomplished thanks to coincidence detection (CD) mechanisms enabled by the presence of synaptic delays that align temporally disparate inputs for effective integration. Computational studies on spiking neural networks further highlight the significance of delays for achieving spatio-temporal pattern recognition with pure feed-forward neural networks, without the need of resorting to recurrent architectures. In this work, we present "DenRAM", the first realization of a feed-forward spiking neural network with dendritic compartments, implemented using analog electronic circuits integrated into a 130 nm technology node and coupled with Resistive Random Access Memory (RRAM) technology. DenRAM's dendritic circuits use RRAM devices to implement both delays and synaptic weights in the network. By configuring the RRAM devices to reproduce bio-realistic timescales, and by exploiting their heterogeneity we experimentally demonstrate DenRAM's ability to replicate synaptic delay profiles, and to efficiently implement CD for spatio-temporal pattern recognition. To validate the architecture, we conduct comprehensive system-level simulations on two representative temporal benchmarks, demonstrating DenRAM's resilience to analog hardware noise, and its superior accuracy compared to recurrent architectures with an equivalent number of parameters. DenRAM not only brings rich temporal processing capabilities to neuromorphic architectures, but also reduces the memory footprint of edge devices, warrants high accuracy on temporal benchmarks, and represents a significant step-forward in low-power real-time signal processing technologies.

Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing

Artificial intelligence (AI) edge devices prefer employing high-capacity nonvolatile compute-in-memory (CIM) to achieve high energy efficiency and rapid wakeup-to-response with sufficient accuracy. Most previous works are based on either memristor-based CIMs, which suffer from accuracy loss and do not support training as a result of limited endurance, or digital static random-access memory (SRAM)-based CIMs, which suffer from large area requirements and volatile storage. We report an AI edge processor that uses a memristor-SRAM CIM-fusion scheme to simultaneously exploit the high accuracy of the digital SRAM CIM and the high energy-efficiency and storage density of the resistive random-access memory memristor CIM. This also enables adaptive local training to accommodate personalized characterization and user environment. The fusion processor achieved high CIM capacity, short wakeup-to-response latency (392 microseconds), high peak energy efficiency (77.64 teraoperations per second per watt), and robust accuracy (<0.5% accuracy loss). This work demonstrates that memristor technology has moved beyond in-lab development stages and now has manufacturability for AI edge processors.

Modeling of Self-Aligned Selector Based on Ultra-Thin Metal Oxide for Resistive Random-Access Memory (RRAM) Crossbar Arrays

Resistive random-access memory (RRAM) is a crucial element for next-generation large-scale memory arrays, analogue neuromorphic computing and energy-efficient System-on-Chip applications. For these applications, RRAM elements are arranged into Crossbar arrays, where rectifying selector devices are required for correct read operation of the memory cells. One of the key advantages of RRAM is its high scalability due to the filamentary mechanism of resistive switching, as the cell conductivity is not dependent on the cell area. Thus, a selector device becomes a limiting factor in Crossbar arrays in terms of scalability, as its area exceeds the minimal possible area of an RRAM cell. We propose a tunnel diode selector, which is self-aligned with an RRAM cell and, thus, occupies the same area. In this study, we address the theoretical and modeling aspects of creating a self-aligned selector with optimal parameters to avoid any deterioration of RRAM cell performance. We investigate the possibilities of using a tunnel diode based on single- and double-layer dielectrics and determine their optimal physical properties to be used in an HfOx-based RRAM Crossbar array.

A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects

A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector-matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.

MoOx Synaptic Memristor with Programmable Multilevel Conductance for Reliable Neuromorphic Hardware

Memristor holds great potential for enabling next-generation neuromorphic computing hardware. Controlling the interfacial characteristics of the device is critical for seamlessly integrating and replicating the synaptic dynamic behaviors; however, it is commonly overlooked. Herein, we report the straightforward oxidation of a Mo electrode in air to design MoOx memristors that exhibit nonvolatile ultrafast switching (0.6-0.8 mV/decade, <1 mV/decade) with a high on/off ratio (>104), a long durability (>104 s), a low power consumption (17.9 μW), excellent device-to-device uniformity, ingeniously synaptic behavior, and finely programmable multilevel analog switching. The analyzed physical mechanism of the observed resistive switching behavior might be the conductive filaments formed by the oxygen vacancies. Intriguingly, upon organization into memristor-based crossbar arrays, in addition to simulated multipattern memorization, edge detection on random images can be implemented well by parallel processing of pixels using a 3 × 3 × 2 array of Prewitt filter groups. These are vital functions for neural system hardware in efficient in-memory computing neural systems with massive parallelism beyond a von Neumann architecture.

A Fully-Integrated Memristor Chip for Edge Learning

The fully-integrated memristor chip for edge learning provides a solid foundation for neural network computation. The fully-integrated memristor chip enables efficient object recognition in noisy backgrounds while minimizing energy consumption. The computing-in-memory chip represents an innovative and interdisciplinary technology that extends beyond multiple research domains.

Memristor-Based Neuromorphic Chips

In the era of information, characterized by an exponential growth in data volume and an escalating level of data abstraction, there has been a substantial focus on brain-like chips, which are known for their robust processing power and energy-efficient operation. Memristors are widely acknowledged as the optimal electronic devices for the realization of neuromorphic computing, due to their innate ability to emulate the interconnection and information transfer processes witnessed among neurons. This review paper focuses on memristor-based neuromorphic chips, which provide an extensive description of the working principle and characteristic features of memristors, along with their applications in the realm of neuromorphic chips. Subsequently, a thorough discussion of the memristor array, which serves as the pivotal component of the neuromorphic chip, as well as an examination of the present mainstream neural networks, is delved. Furthermore, the design of the neuromorphic chip is categorized into three crucial sections, including synapse-neuron cores, networks on chip (NoC), and neural network design. Finally, the key performance metrics of the chip is highlighted, as well as the key metrics related to the memristor devices are employed to realize both the synaptic and neuronal components.

Resistive Memory Devices at the Thinnest Limit: Progress and Challenges

The Si-based integrated circuits industry has been developing for more than half a century, by focusing on the scaling-down of transistor. However, the miniaturization of transistors will soon reach its physical limits, thereby requiring novel material and device technologies. Resistive memory is a promising candidate for in-memory computing and energy-efficient synaptic devices that can satisfy the computational demands of the future applications. However, poor cycle-to-cycle and device-to-device uniformities hinder its mass production. 2D materials, as a new type of semiconductor, is successfully employed in various micro/nanoelectronic devices and have the potential to drive future innovation in resistive memory technology. This review evaluates the potential of using the thinnest advanced materials, that is, monolayer 2D materials, for memristor or memtransistor applications, including resistive switching behavior and atomic mechanism, high-frequency device performances, and in-memory computing/neuromorphic computing applications. The scaling-down advantages of promising monolayer 2D materials including graphene, transition metal dichalcogenides, and hexagonal boron nitride are presented. Finally, the technical challenges of these atomic devices for practical applications are elaborately discussed. The study of monolayer-2D-material-based resistive memory is expected to play a positive role in the exploration of beyond-Si electronic technologies.

Silicon-Compatible Ferroelectric Tunnel Junctions with a SiO2/Hf0.5Zr0.5O2 Composite Barrier as Low-Voltage and Ultra-High-Speed Memristors

The big data era requires ultrafast, low-power, and silicon-compatible materials and devices for information storage and processing. Here, ferroelectric tunnel junctions (FTJs) based on SiO2/Hf0.5Zr0.5O2 composite barrier and both conducting electrodes are designed and fabricated on Si substrates. The FTJ achieves the fastest write speed of 500 ps under 5 V (2 orders of magnitude faster than reported silicon-compatible FTJs) or 10 ns speed at a low voltage of 1.5 V (the lowest voltage among FTJs at similar speeds), low write current density of 1.3 × 104 A cm-2, 8 discrete states, good retention > 105 s at 85 °C, and endurance > 107. In addition, it provides a large read current (88 A cm-2) at 0.1 V, 2 orders of magnitude larger than reported FTJs. Interestingly, in FTJ-based synapses, gradually tunable conductance states (128 states) with high linearity (<1) are obtained by 10 ns pulses of <1.2 V, and a high accuracy of 91.8% in recognizing fashion product images is achieved by online neural network simulations. These results highlight that silicon-compatible HfO2-based FTJs are promising for high-performance nonvolatile memories and electrical synapses.

Stochastic neuro-fuzzy system implemented in memristor crossbar arrays

Neuro-symbolic artificial intelligence has garnered considerable attention amid increasing industry demands for high-performance neural networks that are interpretable and adaptable to previously unknown problem domains with minimal reconfiguration. However, implementing neuro-symbolic hardware is challenging due to the complexity in symbolic knowledge representation and calculation. We experimentally demonstrated a memristor-based neuro-fuzzy hardware based on TiN/TaOx/HfOx/TiN chips that is superior to its silicon-based counterpart in terms of throughput and energy efficiency by using array topological structure for knowledge representation and physical laws for computing. Intrinsic memristor variability is fully exploited to increase robustness in knowledge representation. A hybrid in situ training strategy is proposed for error minimizing in training. The hardware adapts easier to a previously unknown environment, achieving ~6.6 times faster convergence and ~6 times lower error than deep learning. The hardware energy efficiency is over two orders of magnitude greater than field-programmable gate arrays. This research greatly extends the capability of memristor-based neuromorphic computing systems in artificial intelligence.

Hardware implementation of memristor-based artificial neural networks

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

Technology and Integration Roadmap for Optoelectronic Memristor

Optoelectronic memristors (OMs) have emerged as a promising optoelectronic Neuromorphic computing paradigm, opening up new opportunities for neurosynaptic devices and optoelectronic systems. These OMs possess a range of desirable features including minimal crosstalk, high bandwidth, low power consumption, zero latency, and the ability to replicate crucial neurological functions such as vision and optical memory. By incorporating large-scale parallel synaptic structures, OMs are anticipated to greatly enhance high-performance and low-power in-memory computing, effectively overcoming the limitations of the von Neumann bottleneck. However, progress in this field necessitates a comprehensive understanding of suitable structures and techniques for integrating low-dimensional materials into optoelectronic integrated circuit platforms. This review aims to offer a comprehensive overview of the fundamental performance, mechanisms, design of structures, applications, and integration roadmap of optoelectronic synaptic memristors. By establishing connections between materials, multilayer optoelectronic memristor units, and monolithic optoelectronic integrated circuits, this review seeks to provide insights into emerging technologies and future prospects that are expected to drive innovation and widespread adoption in the near future.

Electrochemical random-access memory: recent advances in materials, devices, and systems towards neuromorphic computing

Artificial neural networks (ANNs), inspired by the human brain's network of neurons and synapses, enable computing machines and systems to execute cognitive tasks, thus embodying artificial intelligence (AI). Since the performance of ANNs generally improves with the expansion of the network size, and also most of the computation time is spent for matrix operations, AI computation have been performed not only using the general-purpose central processing unit (CPU) but also architectures that facilitate parallel computation, such as graphic processing units (GPUs) and custom-designed application-specific integrated circuits (ASICs). Nevertheless, the substantial energy consumption stemming from frequent data transfers between processing units and memory has remained a persistent challenge. In response, a novel approach has emerged: an in-memory computing architecture harnessing analog memory elements. This innovation promises a notable advancement in energy efficiency. The core of this analog AI hardware accelerator lies in expansive arrays of non-volatile memory devices, known as resistive processing units (RPUs). These RPUs facilitate massively parallel matrix operations, leading to significant enhancements in both performance and energy efficiency. Electrochemical random-access memory (ECRAM), leveraging ion dynamics in secondary-ion battery materials, has emerged as a promising candidate for RPUs. ECRAM achieves over 1000 memory states through precise ion movement control, prompting early-stage research into material stacks such as mobile ion species and electrolyte materials. Crucially, the analog states in ECRAMs update symmetrically with pulse number (or voltage polarity), contributing to high network performance. Recent strides in device engineering in planar and three-dimensional structures and the understanding of ECRAM operation physics have marked significant progress in a short research period. This paper aims to review ECRAM material advancements through literature surveys, offering a systematic discussion on engineering assessments for ion control and a physical understanding of array-level demonstrations. Finally, the review outlines future directions for improvements, co-optimization, and multidisciplinary collaboration in circuits, algorithms, and applications to develop energy-efficient, next-generation AI hardware systems.

Programming memristor arrays with arbitrarily high precision for analog computing

In-memory computing represents an effective method for modeling complex physical systems that are typically challenging for conventional computing architectures but has been hindered by issues such as reading noise and writing variability that restrict scalability, accuracy, and precision in high-performance computations. We propose and demonstrate a circuit architecture and programming protocol that converts the analog computing result to digital at the last step and enables low-precision analog devices to perform high-precision computing. We use a weighted sum of multiple devices to represent one number, in which subsequently programmed devices are used to compensate for preceding programming errors. With a memristor system-on-chip, we experimentally demonstrate high-precision solutions for multiple scientific computing tasks while maintaining a substantial power efficiency advantage over conventional digital approaches.

Polarization-Dependent Memory and Erasure in Quantum Dots/Graphene Synaptic Devices

We demonstrate excitatory and inhibitory properties in a single heterostructure consisting of two quantum dots/graphene synaptic elements using linearly polarized monochromatic light. Perovskite quantum dots and PbS quantum dots were used to increase and decrease photocurrent weights, respectively. The polarization-dependent photocurrent was realized by adding a polarizer in the middle of the PbS quantum dots/graphene and perovskite quantum dots/graphene elements. When linearly polarized light passed through the polarizer, both the lower excitatory and upper inhibitory devices were activated, with the lower device with the stronger response dominating to increase the current weight. In contrast, the polarized light was blocked by the polarizer, and the above device was only operated, reducing the current weight. Furthermore, two orthogonal polarizations of light were used to perform the sequential processes of potentiation and habituation. By adjustment of the polarization angle of light, not only the direction of the current weight but also its level was altered.

Multifunctional HfAlO thin film: Ferroelectric tunnel junction and resistive random access memory

This study presents findings indicating that the ferroelectric tunnel junction (FTJ) or resistive random-access memory (RRAM) in one cell can be intentionally selected depending on the application. The HfAlO film annealed at 700 °C shows stable FTJ characteristics and can be converted into RRAM by forming a conductive filament inside the same cell, that is, the process of intentionally forming a conductive filament is the result of defect generation and redistribution, and applying compliance current prior to a hard breakdown event of the dielectric film enables subsequent RRAM operation. The converted RRAM demonstrated good memory performance. Through current-voltage fitting, it was confirmed that the two resistance states of the FTJ and RRAM had different transport mechanisms. In the RRAM, the 1/f noise power of the high-resistance state (HRS) was about ten times higher than that of the low-resistance state (LRS). This is because the noise components increase due to the additional current paths in the HRS. The 1/f noise power according to resistance states in the FTJ was exactly the opposite result from the case of the RRAM. This is because the noise component due to the Poole-Frenkel emission is added to the noise component due to the tunneling current in the LRS. In addition, we confirmed the potentiation and depression characteristics of the two devices and further evaluated the accuracy of pattern recognition through a simulation by considering a dataset from the Modified National Institute of Standards and Technology.

Toward a Brain-Neuromorphics Interface

Brain-computer interfaces (BCIs) that enable human-machine interaction have immense potential in restoring or augmenting human capabilities. Traditional BCIs are realized based on complementary metal-oxide-semiconductor (CMOS) technologies with complex, bulky, and low biocompatible circuits, and suffer with the low energy efficiency of the von Neumann architecture. The brain-neuromorphics interface (BNI) would offer a promising solution to advance the BCI technologies and shape the interactions with machineries. Neuromorphic devices and systems are able to provide substantial computation power with extremely high energy-efficiency by implementing in-materia computing such as in situ vector-matrix multiplication (VMM) and physical reservoir computing. Recent progresses on integrating neuromorphic components with sensing and/or actuating modules, give birth to the neuromorphic afferent nerve, efferent nerve, sensorimotor loop, and so on, which has advanced the technologies for future neurorobotics by achieving sophisticated sensorimotor capabilities as the biological system. With the development on the compact artificial spiking neuron and bioelectronic interfaces, the seamless communication between a BNI and a bioentity is reasonably expectable. In this review, the upcoming BNIs are profiled by introducing the brief history of neuromorphics, reviewing the recent progresses on related areas, and discussing the future advances and challenges that lie ahead.

Low-dimensional nanostructures for monolithic 3D-integrated flexible and stretchable electronics

Flexible/stretchable electronics, which are characterized by their ultrathin design, lightweight structure, and excellent mechanical robustness and conformability, have garnered significant attention due to their unprecedented potential in healthcare, advanced robotics, and human-machine interface technologies. An increasing number of low-dimensional nanostructures with exceptional mechanical, electronic, and/or optical properties are being developed for flexible/stretchable electronics to fulfill the functional and application requirements of information sensing, processing, and interactive loops. Compared to the traditional single-layer format, which has a restricted design space, a monolithic three-dimensional (M3D) integrated device architecture offers greater flexibility and stretchability for electronic devices, achieving a high-level of integration to accommodate the state-of-the-art design targets, such as skin-comfort, miniaturization, and multi-functionality. Low-dimensional nanostructures possess small size, unique characteristics, flexible/elastic adaptability, and effective vertical stacking capability, boosting the advancement of M3D-integrated flexible/stretchable systems. In this review, we provide a summary of the typical low-dimensional nanostructures found in semiconductor, interconnect, and substrate materials, and discuss the design rules of flexible/stretchable devices for intelligent sensing and data processing. Furthermore, artificial sensory systems in 3D integration have been reviewed, highlighting the advancements in flexible/stretchable electronics that are deployed with high-density, energy-efficiency, and multi-functionalities. Finally, we discuss the technical challenges and advanced methodologies involved in the design and optimization of low-dimensional nanostructures, to achieve monolithic 3D-integrated flexible/stretchable multi-sensory systems.

Proposition of Adaptive Read Bias: A Solution to Overcome Power and Scaling Limitations in Ferroelectric-Based Neuromorphic System

Hardware neuromorphic systems are crucial for the energy-efficient processing of massive amounts of data. Among various candidates, hafnium oxide ferroelectric tunnel junctions (FTJs) are highly promising for artificial synaptic devices. However, FTJs exhibit non-ideal characteristics that introduce variations in synaptic weights, presenting a considerable challenge in achieving high-performance neuromorphic systems. The primary objective of this study is to analyze the origin and impact of these variations in neuromorphic systems. The analysis reveals that the major bottleneck in achieving a high-performance neuromorphic system is the dynamic variation, primarily caused by the intrinsic 1/f noise of the device. As the device area is reduced and the read bias (VRead ) is lowered, the intrinsic noise of the FTJs increases, presenting an inherent limitation for implementing area- and power-efficient neuromorphic systems. To overcome this limitation, an adaptive read-biasing (ARB) scheme is proposed that applies a different VRead to each layer of the neuromorphic system. By exploiting the different noise sensitivities of each layer, the ARB method demonstrates significant power savings of 61.3% and a scaling effect of 91.9% compared with conventional biasing methods. These findings contribute significantly to the development of more accurate, efficient, and scalable neuromorphic systems.

Adapted MLP-Mixer network based on crossbar arrays of fast and multilevel switching (Co-Fe-B)x(LiNbO3)100-x nanocomposite memristors

MLP-Mixer based on multilayer perceptrons (MLPs) is a novel architecture of a neuromorphic computing system (NCS) introduced for image classification tasks without convolutional layers. Its software realization demonstrates high classification accuracy, although the number of trainable weights is relatively low. One more promising way of improving the NCS performance, especially in terms of power consumption, is its hardware realization using memristors. Therefore, in this work, we proposed an NCS with an adapted MLP-Mixer architecture and memristive weights. For this purpose, we used a passive crossbar array of (Co-Fe-B)x(LiNbO3)100-x memristors. Firstly, we studied the characteristics of such memristors, including their minimal resistive switching time, which was extrapolated to be in the picosecond range. Secondly, we created a fully hardware NCS with memristive weights that are capable of classification of simple 4-bit vectors. The system was shown to be robust to noise introduction in the input patterns. Finally, we used experimental memristive characteristics to simulate an adapted MLP-Mixer architecture that demonstrated a classification accuracy of (94.7 ± 0.3)% on the Modified National Institute of Standards and Technology (MNIST) dataset. The obtained results are the first steps toward the realization of memristive NCS with a promising MLP-Mixer architecture.

Powering AI at the edge: A robust, memristor-based binarized neural network with near-memory computing and miniaturized solar cell

Memristor-based neural networks provide an exceptional energy-efficient platform for artificial intelligence (AI), presenting the possibility of self-powered operation when paired with energy harvesters. However, most memristor-based networks rely on analog in-memory computing, necessitating a stable and precise power supply, which is incompatible with the inherently unstable and unreliable energy harvesters. In this work, we fabricated a robust binarized neural network comprising 32,768 memristors, powered by a miniature wide-bandgap solar cell optimized for edge applications. Our circuit employs a resilient digital near-memory computing approach, featuring complementarily programmed memristors and logic-in-sense-amplifier. This design eliminates the need for compensation or calibration, operating effectively under diverse conditions. Under high illumination, the circuit achieves inference performance comparable to that of a lab bench power supply. In low illumination scenarios, it remains functional with slightly reduced accuracy, seamlessly transitioning to an approximate computing mode. Through image classification neural network simulations, we demonstrate that misclassified images under low illumination are primarily difficult-to-classify cases. Our approach lays the groundwork for self-powered AI and the creation of intelligent sensors for various applications in health, safety, and environment monitoring.

Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory

Data-centric applications are pushing the limits of energy-efficiency in today's computing systems, including those based on phase-change memory (PCM). This technology must achieve low-power and stable operation at nanoscale dimensions to succeed in high-density memory arrays. Here we use a novel combination of phase-change material superlattices and nanocomposites (based on Ge4Sb6Te7), to achieve record-low power density ≈ 5 MW/cm2 and ≈ 0.7 V switching voltage (compatible with modern logic processors) in PCM devices with the smallest dimensions to date (≈ 40 nm) for a superlattice technology on a CMOS-compatible substrate. These devices also simultaneously exhibit low resistance drift with 8 resistance states, good endurance (≈ 2 × 108 cycles), and fast switching (≈ 40 ns). The efficient switching is enabled by strong heat confinement within the superlattice materials and the nanoscale device dimensions. The microstructural properties of the Ge4Sb6Te7 nanocomposite and its high crystallization temperature ensure the fast-switching speed and stability in our superlattice PCM devices. These results re-establish PCM technology as one of the frontrunners for energy-efficient data storage and computing.

Self-Assembly of Delta-Formamidinium Lead Iodide Nanoparticles to Nanorods: Study of Memristor Properties and Resistive Switching Mechanism

In the quest for advanced memristor technologies, this study introduces the synthesis of delta-formamidinium lead iodide (δ-FAPbI3 ) nanoparticles (NPs) and their self-assembly into nanorods (NRs). The formation of these NRs is facilitated by iodide vacancies, promoting the fusion of individual NPs at higher concentrations. Notably, these NRs exhibit robust stability under ambient conditions, a distinctive advantage attributed to the presence of capping ligands and a crystal lattice structured around face-sharing octahedra. When employed as the active layer in resistive random-access memory devices, these NRs demonstrate exceptional bipolar switching properties. A remarkable on/off ratio (105 ) is achieved, surpassing the performances of previously reported low-dimensional perovskite derivatives and α-FAPbI3 NP-based devices. This enhanced performance is attributed to the low off-state current owing to the reduced number of halide vacancies, intrinsic low dimensionality, and the parallel alignment of NRs on the FTO substrate. This study not only provides significant insights into the development of superior materials for memristor applications but also opens new avenues for exploring low-dimensional perovskite derivatives in advanced electronic devices.

Purely self-rectifying memristor-based passive crossbar array for artificial neural network accelerators

Memristor-integrated passive crossbar arrays (CAs) could potentially accelerate neural network (NN) computations, but studies on these devices are limited to software-based simulations owing to their poor reliability. Herein, we propose a self-rectifying memristor-based 1 kb CA as a hardware accelerator for NN computations. We conducted fully hardware-based single-layer NN classification tasks involving the Modified National Institute of Standards and Technology database using the developed passive CA, and achieved 100% classification accuracy for 1500 test sets. We also investigated the influences of the defect-tolerance capability of the CA, impact of the conductance range of the integrated memristors, and presence or absence of selection functionality in the integrated memristors on the image classification tasks. We offer valuable insights into the behavior and performance of CA devices under various conditions and provide evidence of the practicality of memristor-integrated passive CAs as hardware accelerators for NN applications.

Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems

The brain's connectivity is locally dense and globally sparse, forming a small-world graph-a principle prevalent in the evolution of various species, suggesting a universal solution for efficient information routing. However, current artificial neural network circuit architectures do not fully embrace small-world neural network models. Here, we present the neuromorphic Mosaic: a non-von Neumann systolic architecture employing distributed memristors for in-memory computing and in-memory routing, efficiently implementing small-world graph topologies for Spiking Neural Networks (SNNs). We've designed, fabricated, and experimentally demonstrated the Mosaic's building blocks, using integrated memristors with 130 nm CMOS technology. We show that thanks to enforcing locality in the connectivity, routing efficiency of Mosaic is at least one order of magnitude higher than other SNN hardware platforms. This is while Mosaic achieves a competitive accuracy in a variety of edge benchmarks. Mosaic offers a scalable approach for edge systems based on distributed spike-based computing and in-memory routing.

Self-Rectifying Memristors for Three-Dimensional In-Memory Computing

Costly data movement in terms of time and energy in traditional von Neumann systems is exacerbated by emerging information technologies related to artificial intelligence. In-memory computing (IMC) architecture aims to address this problem. Although the IMC hardware prototype represented by a memristor is developed rapidly and performs well, the sneak path issue is a critical and unavoidable challenge prevalent in large-scale and high-density crossbar arrays, particularly in three-dimensional (3D) integration. As a perfect solution to the sneak-path issue, a self-rectifying memristor (SRM) is proposed for 3D integration because of its superior integration density. To date, SRMs have performed well in terms of power consumption (aJ level) and scalability (>102  Mbit). Moreover, SRM-configured 3D integration is considered an ideal hardware platform for 3D IMC. This review focuses on the progress in SRMs and their applications in 3D memory, IMC, neuromorphic computing, and hardware security. The advantages, disadvantages, and optimization strategies of SRMs in diverse application scenarios are illustrated. Challenges posed by physical mechanisms, fabrication processes, and peripheral circuits, as well as potential solutions at the device and system levels, are also discussed.

In-memory analog solution of compressed sensing recovery in one step

Modern analog computing, by gaining momentum from nonvolatile resistive memory devices, deals with matrix computations. In-memory analog computing has been demonstrated for solving some basic but ordinary matrix problems in one step. Among the more complicated matrix problems, compressed sensing (CS) is a prominent example, whose recovery algorithms feature high-order matrix operations and hardware-unfriendly nonlinear functions. In light of the local competitive algorithm (LCA), here, we present a closed-loop, continuous-time resistive memory circuit for solving CS recovery in one step. Recovery of one-dimensional (1D) sparse signal and 2D compressive images has been experimentally demonstrated, showing elapsed times around few microseconds and normalized mean squared errors of 10-2. The LCA circuit is one or two orders of magnitude faster than conventional digital approaches. It also substantially outperforms other (electronic or exotically photonic) analog CS recovery methods in terms of speed, energy, and fidelity, thus representing a highly promising technology for real-time CS applications.

Reconfigurable Neuromorphic Computing: Materials, Devices, and Integration

Neuromorphic computing has been attracting ever-increasing attention due to superior energy efficiency, with great promise to promote the next wave of artificial general intelligence in the post-Moore era. Current approaches are, however, broadly designed for stationary and unitary assignments, thus encountering reluctant interconnections, power consumption, and data-intensive computing in that domain. Reconfigurable neuromorphic computing, an on-demand paradigm inspired by the inherent programmability of brain, can maximally reallocate finite resources to perform the proliferation of reproducibly brain-inspired functions, highlighting a disruptive framework for bridging the gap between different primitives. Although relevant research has flourished in diverse materials and devices with novel mechanisms and architectures, a precise overview remains blank and urgently desirable. Herein, the recent strides along this pursuit are systematically reviewed from material, device, and integration perspectives. At the material and device level, one comprehensively conclude the dominant mechanisms for reconfigurability, categorized into ion migration, carrier migration, phase transition, spintronics, and photonics. Integration-level developments for reconfigurable neuromorphic computing are also exhibited. Finally, a perspective on the future challenges for reconfigurable neuromorphic computing is discussed, definitely expanding its horizon for scientific communities.

Moiré synaptic transistor with room-temperature neuromorphic functionality

Moiré quantum materials host exotic electronic phenomena through enhanced internal Coulomb interactions in twisted two-dimensional heterostructures1-4. When combined with the exceptionally high electrostatic control in atomically thin materials5-8, moiré heterostructures have the potential to enable next-generation electronic devices with unprecedented functionality. However, despite extensive exploration, moiré electronic phenomena have thus far been limited to impractically low cryogenic temperatures9-14, thus precluding real-world applications of moiré quantum materials. Here we report the experimental realization and room-temperature operation of a low-power (20 pW) moiré synaptic transistor based on an asymmetric bilayer graphene/hexagonal boron nitride moiré heterostructure. The asymmetric moiré potential gives rise to robust electronic ratchet states, which enable hysteretic, non-volatile injection of charge carriers that control the conductance of the device. The asymmetric gating in dual-gated moiré heterostructures realizes diverse biorealistic neuromorphic functionalities, such as reconfigurable synaptic responses, spatiotemporal-based tempotrons and Bienenstock-Cooper-Munro input-specific adaptation. In this manner, the moiré synaptic transistor enables efficient compute-in-memory designs and edge hardware accelerators for artificial intelligence and machine learning.

Reliable Memristive Synapses Based on Parylene-MoOx Nanocomposites for Neuromorphic Applications

Memristive devices, known for their nonvolatile resistive switching, are promising components for next-generation neuromorphic computing systems, which mimic the brain's neural architecture. Specifically, these devices are well-suited for functioning as artificial synapses due to their analogue tunability and low energy consumption. However, the improvement of their performance and reliability remains a pressing challenge. In this study, we report the development and comprehensive characterization of memristive devices based on a parylene-MoOx (PPX-Mo) nanocomposite layer, which exhibit improved characteristics over their parylene-based counterparts: lower switching voltage and energy, smaller dispersion, and better resistive plasticity. A robust statistical analysis identified the optimal synthesis parameters for these devices, providing valuable insights for future device optimization. The most probable resistive switching mechanism of the devices is proposed. By successfully integrating these memristors into a neuromorphic computing model and showcasing their scalability in crossbar geometry, we demonstrate their potential as functional artificial synapses. The results obtained from this study can be useful for the development of hardware-brain-inspired computational systems.

Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks

Safety-critical sensory applications, like medical diagnosis, demand accurate decisions from limited, noisy data. Bayesian neural networks excel at such tasks, offering predictive uncertainty assessment. However, because of their probabilistic nature, they are computationally intensive. An innovative solution utilizes memristors' inherent probabilistic nature to implement Bayesian neural networks. However, when using memristors, statistical effects follow the laws of device physics, whereas in Bayesian neural networks, those effects can take arbitrary shapes. This work overcome this difficulty by adopting a variational inference training augmented by a "technological loss", incorporating memristor physics. This technique enabled programming a Bayesian neural network on 75 crossbar arrays of 1,024 memristors, incorporating CMOS periphery for in-memory computing. The experimental neural network classified heartbeats with high accuracy, and estimated the certainty of its predictions. The results reveal orders-of-magnitude improvement in inference energy efficiency compared to a microcontroller or an embedded graphics processing unit performing the same task.

Emerging Robust Polymer Materials for High-Performance Two-Terminal Resistive Switching Memory

Facing the era of information explosion and the advent of artificial intelligence, there is a growing demand for information technologies with huge storage capacity and efficient computer processing. However, traditional silicon-based storage and computing technology will reach their limits and cannot meet the post-Moore information storage requirements of ultrasmall size, ultrahigh density, flexibility, biocompatibility, and recyclability. As a response to these concerns, polymer-based resistive memory materials have emerged as promising candidates for next-generation information storage and neuromorphic computing applications, with the advantages of easy molecular design, volatile and non-volatile storage, flexibility, and facile fabrication. Herein, we first summarize the memory device structures, memory effects, and memory mechanisms of polymers. Then, the recent advances in polymer resistive switching materials, including single-component polymers, polymer mixtures, 2D covalent polymers, and biomacromolecules for resistive memory devices, are highlighted. Finally, the challenges and future prospects of polymer memory materials and devices are discussed. Advances in polymer-based memristors will open new avenues in the design and integration of high-performance switching devices and facilitate their application in future information technology.

Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

Bulk-Switching Memristor-Based Compute-In-Memory Module for Deep Neural Network Training

The constant drive to achieve higher performance in deep neural networks (DNNs) has led to the proliferation of very large models. Model training, however, requires intensive computation time and energy. Memristor-based compute-in-memory (CIM) modules can perform vector-matrix multiplication (VMM) in place and in parallel, and have shown great promises in DNN inference applications. However, CIM-based model training faces challenges due to non-linear weight updates, device variations, and low-precision. In this work, a mixed-precision training scheme is experimentally implemented to mitigate these effects using a bulk-switching memristor-based CIM module. Low-precision CIM modules are used to accelerate the expensive VMM operations, with high-precision weight updates accumulated in digital units. Memristor devices are only changed when the accumulated weight update value exceeds a pre-defined threshold. The proposed scheme is implemented with a system-onchip of fully integrated analog CIM modules and digital sub-systems, showing fast convergence of LeNet training to 97.73%. The efficacy of training larger models is evaluated using realistic hardware parameters and verifies that CIM modules can enable efficient mix-precision DNN training with accuracy comparable to full-precision software-trained models. Additionally, models trained on chip are inherently robust to hardware variations, allowing direct mapping to CIM inference chips without additional re-training.

Neural inference at the frontier of energy, space, and time

Computing, since its inception, has been processor-centric, with memory separated from compute. Inspired by the organic brain and optimized for inorganic silicon, NorthPole is a neural inference architecture that blurs this boundary by eliminating off-chip memory, intertwining compute with memory on-chip, and appearing externally as an active memory chip. NorthPole is a low-precision, massively parallel, densely interconnected, energy-efficient, and spatial computing architecture with a co-optimized, high-utilization programming model. On the ResNet50 benchmark image classification network, relative to a graphics processing unit (GPU) that uses a comparable 12-nanometer technology process, NorthPole achieves a 25 times higher energy metric of frames per second (FPS) per watt, a 5 times higher space metric of FPS per transistor, and a 22 times lower time metric of latency. Similar results are reported for the Yolo-v4 detection network. NorthPole outperforms all prevalent architectures, even those that use more-advanced technology processes.

Open-loop analog programmable electrochemical memory array

Emerging memories have been developed as new physical infrastructures for hosting neural networks owing to their low-power analog computing characteristics. However, accurately and efficiently programming devices in an analog-valued array is still largely limited by the intrinsic physical non-idealities of the devices, thus hampering their applications in in-situ training of neural networks. Here, we demonstrate a passive electrochemical memory (ECRAM) array with many important characteristics necessary for accurate analog programming. Different image patterns can be open-loop and serially programmed into our ECRAM array, achieving high programming accuracies without any feedback adjustments. The excellent open-loop analog programmability has led us to in-situ train a bilayer neural network and reached software-like classification accuracy of 99.4% to detect poisonous mushrooms. The training capability is further studied in simulation for large-scale neural networks such as VGG-8. Our results present a new solution for implementing learning functions in an artificial intelligence hardware using emerging memories.

Efficient combinatorial optimization by quantum-inspired parallel annealing in analogue memristor crossbar

Combinatorial optimization problems are prevalent in various fields, but obtaining exact solutions remains challenging due to the combinatorial explosion with increasing problem size. Special-purpose hardware such as Ising machines, particularly memristor-based analog Ising machines, have emerged as promising solutions. However, existing simulate-annealing-based implementations have not fully exploited the inherent parallelism and analog storage/processing features of memristor crossbar arrays. This work proposes a quantum-inspired parallel annealing method that enables full parallelism and improves solution quality, resulting in significant speed and energy improvement when implemented in analog memristor crossbars. We experimentally solved tasks, including unweighted and weighted Max-Cut and traveling salesman problem, using our integrated memristor chip. The quantum-inspired parallel annealing method implemented in memristor-based hardware has demonstrated significant improvements in time- and energy-efficiency compared to previously reported simulated annealing and Ising machine implemented on other technologies. This is because our approach effectively exploits the natural parallelism, analog conductance states, and all-to-all connection provided by memristor technology, promising its potential for solving complex optimization problems with greater efficiency.

Optoelectronic bio-synaptic plasticity on neotype kesterite memristor with switching ratio >104

Optoelectronic memristors hold the most potential for realizing next-generation neuromorphic computation; however, memristive devices that can integrate excellent resistive switching and both electrical-/light-induced bio-synaptic behaviors are still challenging to develop. In this study, an artificial optoelectronic synapse is proposed and realized using a kesterite-based memristor with Cu2ZnSn(S,Se)4 (CZTSSe) as the switching material and Mo/Ag as the back/top electrode. Benefiting from unique electrical features and a bi-layered structure of CZTSSe, the memristor exhibits highly stable nonvolatile resistive switching with excellent spatial uniformity, concentrated Set/Reset voltage distribution (variation <0.08/0.02 V), high On/Off ratio (>104), and long retention time (>104 s). A possible mechanism of the switching behavior in such a device is proposed. Furthermore, these memristors successfully achieve essential bio-synaptic functions under both electrical and various visible light (470-655 nm) stimulations, including electrical-induced excitatory postsynaptic current, paired pulse facilitation, long-term potentiation, long-term depression, spike-timing-dependent plasticity, as well as light-stimulated short-/long-term plasticity and learning-forgetting-relearning process. As such, the proposed neotype kesterite-based memristor demonstrates significant potential in facilitating artificial optoelectronic synapses and enabling neuromorphic computation.