Surface roughness induced electron mobility degradation in InAs nanowires

Self-powered stable high-performance UV-Vis-NIR broadband photodetector based on PVP-Cobalt@Carbon nanofibers/n-GaAs heterojunction

The self-powered PVP-Co@C nanofibers/n-GaAs heterojunction photodetector (HJPD) was fabricated by electrospinning of the nanofibers onto GaAs. An excellent rectification ratio of 6.60 × 106was obtained fromI-Vmeasurements of the device in the dark. TheI-Vmeasurements of the fabricated device under 365 nm, 395 nm and 850 nm lights, as well asI-Vmeasurements in visible light depending on the light intensity, were performed. The HJPD demonstrated excellent photodetection performance in terms of a good responsivity of ∼225 mA W-1(at -1.72 V) and at zero bias, an impressive detectivity of 6.28 × 1012Jones, and a high on/off ratio of 8.38 × 105, all at 365 nm wavelength. In addition, the maximum external quantum efficiency and NPDR values were 3495% (V = -1.72 V) and 2.60 × 1010W-1(V= 0.0 V), respectively, while the minimum NEP value was ∼10-14W.Hz-1/2for 365 nm atV= 0.V volts. The HJPD also exhibited good long-term stability in air after 30 d without any encapsulation.

Highly Efficient ITO-Free Quantum-Dot Light Emitting Diodes via Solution-Processed PEDOT:PSS Semitransparent Electrode

We present a study on the potential use of sulfuric acid-treated poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) as a viable alternative to indium tin oxide (ITO) electrodes in quantum dot light-emitting diodes (QLEDs). ITO, despite its high conductivity and transparency, is known for its disadvantages of being brittle, fragile, and expensive. Furthermore, due to the high hole injection barrier of quantum dots, the need for electrodes with a higher work function is becoming more significant. In this report, we present solution-processed, sulfuric acid-treated PEDOT:PSS electrodes for highly efficient QLEDs. The high work function of the PEDOT:PSS electrodes improved the performance of the QLEDs by facilitating hole injection. We demonstrated the recrystallization and conductivity enhancement of PEDOT:PSS upon sulfuric acid treatment using X-ray photoelectron spectroscopy and Hall measurement. Ultraviolet photoelectron spectroscopy (UPS) analysis of QLEDs showed that sulfuric acid-treated PEDOT:PSS exhibited a higher work function than ITO. The maximum current efficiency and external quantum efficiency based on the PEDOT:PSS electrode QLEDs were measured as 46.53 cd/A and 11.01%, which were three times greater than ITO electrode QLEDs. These findings suggest that PEDOT:PSS can serve as a promising replacement for ITO electrodes in the development of ITO-free QLED devices.

Enhancing the electrical performance of InAs nanowire field-effect transistors by improving the surface and interface properties by coating with thermally oxidized Y2O3

Due to their excellent electrical characteristics, InAs nanowires (NWs) have great potential as conducting channels in integrated circuits. However, the surface effect and loose native oxide coverage can deteriorate the performance of InAs NW transistors. Y₂O₃, a high-k dielectric with low Gibbs free energy, has been proposed to modify the InAs NW surface. Here, we systematically investigate the effect of Y₂O₃ coating on the performance of InAs NW field-effect transistors (FETs). We first explore the influence of the thermal oxidation process of Y₂O₃ on the performance of back-gated FETs. We then observe that the coverage of Y₂O₃/HfO₂ bilayers on the NW decreases the hysteresis (the smallest value reaches 0.1 V), subthreshold swing (SS, down to 169 mV dec^-1) and on-state resistance R_on, and increases the field-effect mobility μ_FE (up to 4876.1 cm² V^-1 s^-1) and the on-off ratio, mainly owing to the passivation effect on the NW surface. Finally, paired top-gated NW FETs with a Y₂O₃/HfO₂ bilayer and a single layer of HfO₂ dielectric are fabricated and compared. The Y₂O₃/HfO₂ bilayer provides better gate control (SS_min = 113 mV dec^-1) under a smaller gate oxide capacitance, with an interface trap density as low as 1.93 × 10¹² eV^-1 cm^-2. The use of the Y₂O₃/HfO₂ stack provides an effective strategy to enhance the performance of III-V-based transistors for future applications.

Analysis of the electron emission characteristics and working mechanism of a planar bottom gate vacuum field emission triode with a nanoscale channel

A planar lateral vacuum field emission triode (VFET) with a nanoscale channel of 80-90 nm was fabricated on a silicon wafer. The nanoscale channel of this vacuum triode was generated by via the electro-forming process (EFP). With the use of a wedge-waist-type conductive film, the distribution of Joule heat during EFP could be guided, which helped to realize the controllable preparation of a nanoscale fissure that served as the vacuum channel. Experimental results revealed that the fabricated device demonstrated good emission characteristics in vacuum and could be operated normally under atmospheric conditions. The triode emission characteristics under atmospheric pressure were preliminarily realized. The field-assisted thermal electron emission for low operating voltage and the Fowler-Nordheim tunneling emission mechanism for voltages greater than the turn-on voltage were used to explain the emission mechanism of the proposed VFET.

Gate Bias Stress Instability and Hysteresis Characteristics of InAs Nanowire Field-Effect Transistors

Because of the excellent electrical properties, III-V semiconductor nanowires are promising building blocks for next-generation electronics; however, their rich surface states inevitably contribute large amounts of charge traps, leading to gate bias stress instability and hysteresis characteristics in nanowire field-effect transistors (FETs). Here, we investigated thoroughly the gate bias stress and hysteresis effects in InAs nanowire FETs. It is observed that the output current decreases together with the threshold voltage shifting to the positive direction when a positive gate bias stress is applied, and vice versa for the negative gate bias stress. For double-sweep transfer characteristics, the significant hysteresis behavior is observed, depending heavily on the sweeping rate and range. On the basis of complementary investigations of these devices, charge traps are confirmed to be the dominant factor for these instability effects. Importantly, the hysteresis can be simulated well by utilizing a combination of the rate equation for electron density and the empirical model for electron mobility. This provides an accurate evaluation of carrier mobility, which is in distinct contrast to the overestimation of mobility when using the transconductance for calculation. All these findings are important for understanding the charge trap dynamics to further enhance the device performance of nanowire FETs.

Thermoelectric Properties of InA Nanowires from Full-Band Atomistic Simulations

In this work we theoretically explore the effect of dimensionality on the thermoelectric power factor of indium arsenide (InA) nanowires by coupling atomistic tight-binding calculations to the Linearized Boltzmann transport formalism. We consider nanowires with diameters from 40 nm (bulk-like) down to 3 nm close to one-dimensional (1D), which allows for the proper exploration of the power factor within a unified large-scale atomistic description across a large diameter range. We find that as the diameter of the nanowires is reduced below d < 10 nm, the Seebeck coefficient increases substantially, as a consequence of strong subband quantization. Under phonon-limited scattering conditions, a considerable improvement of ~6× in the power factor is observed around d = 10 nm. The introduction of surface roughness scattering in the calculation reduces this power factor improvement to ~2×. As the diameter is decreased to d = 3 nm, the power factor is diminished. Our results show that, although low effective mass materials such as InAs can reach low-dimensional behavior at larger diameters and demonstrate significant thermoelectric power factor improvements, surface roughness is also stronger at larger diameters, which takes most of the anticipated power factor advantages away. However, the power factor improvement that can be observed around d = 10 nm could prove to be beneficial as both the Lorenz number and the phonon thermal conductivity are reduced at that diameter. Thus, this work, by using large-scale full-band simulations that span the corresponding length scales, clarifies properly the reasons behind power factor improvements (or degradations) in low-dimensional materials. The elaborate computational method presented can serve as a platform to develop similar schemes for two-dimensional (2D) and three-dimensional (3D) material electronic structures.

Growth of c-plane and m-plane aluminium-doped zinc oxide thin films: epitaxy on flexible substrates with cubic-structure seeds

Manufacturing high-quality zinc oxide (ZnO) devices demands control of the orientation of ZnO materials due to the spontaneous and piezoelectric polarity perpendicular to the c-plane. However, flexible electronic and optoelectronic devices are mostly built on polymers or glass substrates which lack suitable epitaxy seeds for the orientation control. Applying cubic-structure seeds, it was possible to fabricate polar c-plane and nonpolar m-plane aluminium-doped zinc oxide (AZO) films epitaxially on flexible Hastelloy substrates through minimizing the lattice mismatch. The growth is predicted of c-plane and m-plane AZO on cubic buffers with lattice parameters of 3.94-4.63 Å and 5.20-5.60 Å, respectively. The ∼80 nm-thick m-plane AZO film has a resistivity of ∼11.43 ± 0.01 × 10^-4 Ω cm, while the c-plane AZO film shows a resistivity of ∼2.68 ± 0.02 × 10^-4 Ω cm comparable to commercial indium tin oxide films. An abnormally higher carrier concentration in the c-plane than in the m-plane AZO film results from the electrical polarity along the c-axis. The resistivity of the c-plane AZO film drops to the order of 10^-5 Ω cm at 500 K owing to the semiconducting behaviour. Epitaxial AZO films with low resistivities and controllable orientations on flexible substrates offer optimal transparent electrodes and epitaxy seeds for high-performance flexible ZnO devices.

Anomalous Angle-Dependent Magnetotransport Properties of Single InAs Nanowires

We study the magnetotransport properties of single InAs nanowires grown by selective-area metal-organic vapor-phase epitaxy. The semiconducting InAs nanowires exhibit a large positive ordinary magnetoresistance effect. However, a deviation from the corresponding quadratic behavior is observed for an orientation of the applied magnetic field perpendicular to the nanowire axis. This additional contribution to the magnetoresistance can be explained by diffuse boundary scattering of free carriers in the InAs nanowire and results in a reduction of the charge carrier mobility. As a consequence, angle-dependent magnetotransport measurements reveal a highly anomalous behavior. Numerical simulations have been conducted to further investigate the effect of classical boundary scattering in the nanowires. On the basis of the numerical simulations, an empirical description is derived, which yields excellent agreement with the experimental data and allows one to quantify the contribution of boundary scattering to the magnetoresistance effect.

High performance indium oxide nanoribbon FETs: mitigating devices signal variation from batch fabrication

Nanostructured field effect transistor (FET) based sensors have emerged as a powerful bioanalytical technology. However, performance variations across multiple devices and between fabrication batches inevitably exist and present a significant challenge holding back the translation of this cutting-edge technology. We report an optimized and cost-effective fabrication process for high-performance indium oxide nanoribbon FET with a steep subthreshold swing of 80 mV per decade. Through systematic electrical characterizations of 57 indium oxide nanoribbon FETs from different batches, we demonstrate an optimal operation point within the subthreshold regime that mitigates the issue of device-to-device performance variation. A non-linear pH sensing of the fabricated indium oxide nanoribbon FETs is also presented.

A New Analytic Formula for Minority Carrier Decay Length Extraction from Scanning Photocurrent Profiles in Ohmic-Contact Nanowire Devices

Spatially resolved current measurements such as scanning photocurrent microscopy (SPCM) have been extensively applied to investigate carrier transport properties in semiconductor nanowires. A traditional simple-exponential-decay formula based on the assumption of carrier diffusion dominance in the scanning photocurrent profiles can be applied for carrier diffusion length extraction using SPCM in Schottky-contact-based or p-n junction-based devices where large built-in electric fields exist. However, it is also important to study the electric-field dependent transport properties in widely used ohmic-contact nanowire devices where the assumption of carrier diffusion dominance is invalid. Here we derive an analytic formula for scanning photocurrent profiles in such ohmic-contact nanowire devices under uniform applied electric fields and weak optical excitation. Under these operation conditions and the influence of photo-carrier-induced electric field, the scanning photocurrent profile and the carrier spatial distribution strikingly do not share the same functional form. Instead, a surprising new analytic relation between the scanning photocurrent profile and the minority carrier decay length was established. Then the derived analytic formula was validated numerically and experimentally. This analytic formula provides a new fitting method for SPCM profiles to correctly determine the minority carrier decay length, which allows us to quantitatively evaluate the performance of nanowire-based devices.

Improving the electrical properties of InAs nanowire field effect transistors by covering them with Y2O3/HfO2 layers

Quasi-one-dimensional semiconducting materials have attracted increasing attention due to their excellent ability to downscale the size of transistors. However, in quasi-one-dimensional nanowire (NW) transistors, their surface and interface properties play a very important role mainly due to the large surface-to-volume ratio of NWs and surface scattering, which degrade their carrier mobility. Herein, we developed a new method to cover the channel surface of InAs NW field effect transistors (FETs) with Y₂O₃/HfO₂ layers to improve their electrical properties. We successfully fabricated nine FETs and measured their electrical properties, which improve after depositing the Y₂O₃/HfO₂ layers, including an increase in on-state current, decrease in off-state current, increase in transconductance, increase in electron mobility and decrease in subthreshold swing. By comparing the properties of Y₂O₃/HfO₂-covered devices with that of the FETs fabricated without the Y₂O₃ covering or without annealing, we prove that it is the combined Y₂O₃/HfO₂ layers instead of only the Y₂O₃ or HfO₂ layer that improve the electrical properties of the FETs. The Cs-corrected high-resolution scanning transmission electron microscopy study demonstrates that Y can actually diffuse through the native oxide layer (confirmed to be InO_x) and reach the surface of the InAs NWs. Our results indicate that the desirable characteristics of Y₂O₃ and the surface passivation by HfO₂ improve the electrical properties of the InAs NW FETs, in which Y₂O₃ plays an important role to modify and stabilize the interface between the InAs NWs and the outside dielectric layer. Furthermore, this method should also be applicable to other III-V materials.

Graphene-Based Nanoscale Vacuum Channel Transistor

We report the fabrication and electrical performance of nanoscale vacuum channel transistor (NVCT) based on graphene. Ninety-nanometer-width vacuum nano-channel could be precisely fabricated with standard electron beam lithography process. The optimization and treatment of surface damage and adhesive residue on graphene are carried out by ultrasonic cleaning and thermal annealing. Additionally, in situ electric characteristics are directly performed inside a vacuum chamber of scanning electron microscope (SEM) with the nanomanipulator. By modulating the gate voltage, the NVCT could be switched from off-state to on-state, exhibiting an on/off current ratio up to 10² with low working voltages (< 20 V) and leakage current (< 0.5 nA). Furthermore, the nanoscale vacuum channel could enable to scale down the size of vacuum devices with high integration, making NVCT a promising candidate for high speed applications.

Formation Mechanisms of InGaAs Nanowires Produced by a Solid-Source Two-Step Chemical Vapor Deposition

The morphologies and microstructures of Au-catalyzed InGaAs nanowires (NWs) prepared by a two-step solid-source chemical vapor deposition (CVD) method were systematically investigated using scanning electron microscopy (SEM) and high-resolution transmission electron microscopy (HRTEM). The detailed structural characterization and statistical analysis reveal that two specific morphologies are dominant in InGaAs NWs, a zigzag surface morphology and a smooth surface morphology. The zigzag morphology results from the periodic existence of twining structures, and the smooth morphology results from a lack of twining structures. HRTEM images and energy-dispersive X-ray spectroscopy (EDX) indicate that the catalyst heads have two structures, Au₄In and AuIn₂, which produce InGaAs NWs in a cubic phase crystalline form. The growth mechanism of the InGaAs NWs begins with Au nanoparticles melting into small spheres. In atoms are diffused into the Au spheres to form an Au-In alloy. When the concentration of In inside the alloy reaches its saturation point, the In precipitate reacts with Ga and As atoms to form InGaAs at the interface between the catalyst and substrate. Once the InGaAs compound forms, additional precipitation and reactions only occur at the interface of the InGaAs and the catalyst. These results provide a fundamental understanding of the InGaAs NW growth process which is critical to the formation of high-quality InGaAs NWs for various device applications.

Preparation and Characterization of Solution-Processed Nanocrystalline p-Type CuAlO2 Thin-Film Transistors

The development of p-type metal oxide thin-film transistors (TFTs) is far behind the n-type counterparts. Here, p-type CuAlO₂ thin films were deposited by spin coating and annealed in nitrogen atmosphere at different temperature. The effect of post-annealing temperature on the microstructure, chemical compositions, morphology, and optical properties of the thin films was investigated systematically. The phase conversion from a mixture of CuAl₂O₄ and CuO to nanocrystalline CuAlO₂ was achieved when annealing temperature was higher than 900 °C, as well as the transmittance, optical energy band gap, grain size, and surface roughness of the films increase with the increase of annealing temperature. Next, bottom-gate p-type TFTs with CuAlO₂ channel layer were fabricated on SiO₂/Si substrate. It was found that the TFT performance was strongly dependent on the physical properties and the chemical composition of channel layer. The optimized nanocrystalline CuAlO₂ TFT exhibits a threshold voltage of - 1.3 V, a mobility of ~ 0.1 cm² V^-1 s^-1, and a current on/off ratio of ~ 10³. This report on solution-processed p-type CuAlO₂ TFTs represents a significant progress towards low-cost complementary metal oxide semiconductor logic circuits.

Correlation between Electrical Transport and Nanoscale Strain in InAs/In0.6Ga0.4As Core-Shell Nanowires

Free-standing semiconductor nanowires constitute an ideal material system for the direct manipulation of electrical and optical properties by strain engineering. In this study, we present a direct quantitative correlation between electrical conductivity and nanoscale lattice strain of individual InAs nanowires passivated with a thin epitaxial In_0.6Ga_0.4As shell. With an in situ electron microscopy electromechanical testing technique, we show that the piezoresistive response of the nanowires is greatly enhanced compared to bulk InAs, and that uniaxial elastic strain leads to increased conductivity, which can be explained by a strain-induced reduction in the band gap. In addition, we observe inhomogeneity in strain distribution, which could have a reverse effect on the conductivity by increasing the scattering of charge carriers. These results provide a direct correlation of nanoscale mechanical strain and electrical transport properties in free-standing nanostructures.

Chalcogen passivation: an in-situ method to manipulate the morphology and electrical property of GaAs nanowires

Recently, owing to the large surface-area-to-volume ratio of nanowires (NWs), manipulation of their surface states becomes technologically important and being investigated for various applications. Here, an in-situ surfactant-assisted chemical vapor deposition is developed with various chalcogens (e.g. S, Se and Te) as the passivators to enhance the NW growth and to manipulate the controllable p-n conductivity switching of fabricated NW devices. Due to the optimal size effect and electronegativity matching, Se is observed to provide the best NW surface passivation in diminishing the space charge depletion effect induced by the oxide shell and yielding the less p-type (i.e. inversion) or even insulating conductivity, as compared with S delivering the intense p-type conductivity for thin NWs with the diameter of ~30 nm. Te does not only provide the surface passivation, but also dopes the NW surface into n-type conductivity by donating electrons. All of the results can be extended to other kinds of NWs with similar surface effects, resulting in careful device design considerations with appropriate surface passivation for achieving the optimal NW device performances.

Morphological investigations on the growth of defect-rich Bi2Te3 nanorods and their thermoelectric properties

Bi₂Te₃ nanorods (NRs) have been successfully synthesized at different reaction temperatures via a surfactant-assisted hydrothermal method.

Electronic Structure Changes Due to Crystal Phase Switching at the Atomic Scale Limit

The perfect switching between crystal phases with different electronic structure in III-V nanowires allows for the design of superstructures with quantum wells only a single atomic layer wide. However, it has only been indirectly inferred how the electronic structure will vary down to the smallest possible crystal segments. We use low-temperature scanning tunneling microscopy and spectroscopy to directly probe the electronic structure of Zinc blende (Zb) segments in Wurtzite (Wz) InAs nanowires with atomic-scale precision. We find that the major features in the band structure change abruptly down to a single atomic layer level. Distinct Zb electronic structure signatures are observed on both the conduction and valence band sides for the smallest possible Zb segment: a single InAs bilayer. We find evidence of confined states in the region of both single and double bilayer Zb segments indicative of the formation of crystal segment quantum wells due to the smaller band gap of Zb as compared to Wz. In contrast to the internal electronic structure of the nanowire, surface states located in the band gap were found to be only weakly influenced by the presence of the smallest Zb segments. Our findings directly demonstrate the feasibility of crystal phase switching for the ultimate limit of atomistic band structure engineering of quantum confined structures. Further, it indicates that band gap values obtained for the bulk are reasonable to use even for the smallest crystal segments. However, we also find that the suppression of surface and interface states could be necessary in the use of this effect for engineering of future electronic devices.

Transient Clustering of Reaction Intermediates during Wet Etching of Silicon Nanostructures

Wet chemical etching is a key process in fabricating silicon (Si) nanostructures. Currently, wet etching of Si is proposed to occur through the reaction of surface Si atoms with etchant molecules, forming etch intermediates that dissolve directly into the bulk etchant solution. Here, using in situ transmission electron microscopy (TEM), we follow the nanoscale wet etch dynamics of amorphous Si (a-Si) nanopillars in real-time and show that intermediates generated during alkaline wet etching first aggregate as nanoclusters on the Si surface and then detach from the surface before dissolving in the etchant solution. Molecular dynamics simulations reveal that the molecules of etch intermediates remain weakly bound to the hydroxylated Si surface during the etching and aggregate into nanoclusters via surface diffusion instead of directly diffusing into the etchant solution. We confirmed this model experimentally by suppressing the formation of nanoclusters of etch intermediates on the Si surfaces by shielding the hydroxylated Si sites with large ions. These results suggest that the interaction of etch intermediates with etching surfaces controls the solubility of reaction intermediates and is an important parameter in fabricating densely packed clean 3D nanostructures for future generation microelectronics.

Complementary Metal Oxide Semiconductor-Compatible, High-Mobility, ⟨111⟩-Oriented GaSb Nanowires Enabled by Vapor-Solid-Solid Chemical Vapor Deposition

Using CMOS-compatible Pd catalysts, we demonstrated the formation of high-mobility ⟨111⟩-oriented GaSb nanowires (NWs) via vapor-solid-solid (VSS) growth by surfactant-assisted chemical vapor deposition through a complementary experimental and theoretical approach. In contrast to NWs formed by the conventional vapor-liquid-solid (VLS) mechanism, cylindrical-shaped Pd₅Ga₄ catalytic seeds were present in our Pd-catalyzed VSS-NWs. As solid catalysts, stoichiometric Pd₅Ga₄ was found to have the lowest crystal surface energy and thus giving rise to a minimal surface diffusion as well as an optimal in-plane interface orientation at the seed/NW interface for efficient epitaxial NW nucleation. These VSS characteristics led to the growth of slender NWs with diameters down to 26.9 ± 3.5 nm. Over 95% high crystalline quality NWs were grown in ⟨111⟩ orientation for a wide diameter range of between 10 and 70 nm. Back-gated field-effect transistors (FETs) fabricated using the Pd-catalyzed GaSb NWs exhibit a superior peak hole mobility of ∼330 cm² V^-1 s^-1, close to the mobility limit for a NW channel diameter of ∼30 nm with a free carrier concentration of ∼10¹⁸ cm^-3. This suggests that the NWs have excellent homogeneity in phase purity, growth orientation, surface morphology and electrical characteristics. Contact printing process was also used to fabricate large-scale assembly of Pd-catalyzed GaSb NW parallel arrays, confirming the potential constructions and applications of these high-performance electronic devices.

Diameter Dependence of Planar Defects in InP Nanowires

In this work, extensive characterization and complementary theoretical analysis have been carried out on Au-catalyzed InP nanowires in order to understand the planar defect formation as a function of nanowire diameter. From the detailed transmission electron microscopic measurements, the density of stacking faults and twin defects are found to monotonically decrease as the nanowire diameter is decreased to 10 nm, and the chemical analysis clearly indicates the drastic impact of In catalytic supersaturation in Au nanoparticles on the minimized planar defect formation in miniaturized nanowires. Specifically, during the chemical vapor deposition of InP nanowires, a significant amount of planar defects is created when the catalyst seed sizes are increased with the lower degree of In supersaturation as dictated by the Gibbs-Thomson effect, and an insufficient In diffusion (or Au-rich enhancement) would lead to a reduced and non-uniform In precipitation at the NW growing interface. The results presented here provide an insight into the fabrication of "bottom-up" InP NWs with minimized defect concentration which are suitable for various device applications.

High-Performance Wrap-Gated InGaAs Nanowire Field-Effect Transistors with Sputtered Dielectrics

Although wrap-gated nanowire field-effect-transistors (NWFETs) have been explored as an ideal electronic device geometry for low-power and high-frequency applications, further performance enhancement and practical implementation are still suffering from electron scattering on nanowire surface/interface traps between the nanowire channel and gate dielectric as well as the complicated device fabrication scheme. Here, we report the development of high-performance wrap-gated InGaAs NWFETs using conventional sputtered Al₂O₃ layers as gate dielectrics, instead of the typically employed atomic layer deposited counterparts. Importantly, the surface chemical passivation of NW channels performed right before the dielectric deposition is found to significantly alleviate plasma induced defect traps on the NW channel. Utilizing this passivation, the wrap-gated device exhibits superior electrical performances: a high I_ON/I_OFF ratio of ~2 × 10⁶, an extremely low sub-threshold slope of 80 mV/decade and a peak field-effect electron mobility of ~1600 cm²/(Vs) at V_DS = 0.1 V at room temperature, in which these values are even better than the ones of state-of-the-art NWFETs reported so far. By combining sputtering and pre-deposition chemical passivation to achieve high-quality gate dielectrics for wrap-gated NWFETs, the superior gate coupling and electrical performances have been achieved, confirming the effectiveness of our hybrid approach for future advanced electronic devices.

Approaching the Hole Mobility Limit of GaSb Nanowires

In recent years, high-mobility GaSb nanowires have received tremendous attention for high-performance p-type transistors; however, due to the difficulty in achieving thin and uniform nanowires (NWs), there is limited report until now addressing their diameter-dependent properties and their hole mobility limit in this important one-dimensional material system, where all these are essential information for the deployment of GaSb NWs in various applications. Here, by employing the newly developed surfactant-assisted chemical vapor deposition, high-quality and uniform GaSb NWs with controllable diameters, spanning from 16 to 70 nm, are successfully prepared, enabling the direct assessment of their growth orientation and hole mobility as a function of diameter while elucidating the role of sulfur surfactant and the interplay between surface and interface energies of NWs on their electrical properties. The sulfur passivation is found to efficiently stabilize the high-energy NW sidewalls of (111) and (311) in order to yield the thin NWs (i.e., <40 nm in diameters) with the dominant growth orientations of ⟨211⟩ and ⟨110⟩, whereas the thick NWs (i.e., >40 nm in diameters) would grow along the most energy-favorable close-packed planes with the orientation of ⟨111⟩, supported by the approximate atomic models. Importantly, through the reliable control of sulfur passivation, growth orientation and surface roughness, GaSb NWs with the peak hole mobility of ∼400 cm(2)V s(-1) for the diameter of 48 nm, approaching the theoretical limit under the hole concentration of ∼2.2 × 10(18) cm(-3), can be achieved for the first time. All these indicate their promising potency for utilizations in different technological domains.

Modulating Electrical Properties of InAs Nanowires via Molecular Monolayers

In recent years, InAs nanowires have been demonstrated with the excellent electron mobility as well as highly efficient near-infrared and visible photoresponse at room temperature. However, due to the presence of a large amount of surface states that originate from the unstable native oxide, the fabricated nanowire transistors are always operated in the depletion mode with degraded electron mobility, which is not energy-efficient. In this work, instead of the conventional inorganic sulfur or alkanethiol surface passivation, we employ aromatic thiolate (ArS(-))-based molecular monolayers with controllable molecular design and electron density for the surface modification of InAs nanowires (i.e., device channels) by simple wet chemistry. More importantly, besides reliably improving the device performances by enhancing the electron mobility and the current on-off ratio through surface state passivation, the device threshold voltage (VTh) can also be modulated by varying the para-substituent of the monolayers such that the molecule bearing electron-withdrawing groups would significantly shift the VTh towards the positive region for the enhancement mode device operation, in which the effect has been quantified by density functional theory calculations. These findings reveal explicitly the efficient modulation of the InAs nanowires' electronic transport properties via ArS(-)-based molecular monolayers, which further elucidates the technological potency of this ArS(-) surface treatment for future nanoelectronic device fabrication and circuit integration.

Atomic scale surface structure and morphology of InAs nanowire crystal superlattices: the effect of epitaxial overgrowth

While shell growth engineering to the atomic scale is important for tailoring semiconductor nanowires with superior properties, a precise knowledge of the surface structure and morphology at different stages of this type of overgrowth has been lacking. We present a systematic scanning tunneling microscopy (STM) study of homoepitaxial shell growth of twinned superlattices in zinc blende InAs nanowires that transforms {111}A/B-type facets to the nonpolar {110}-type. STM imaging along the nanowires provides information on different stages of the shell growth revealing distinct differences in growth dynamics of the crystal facets and surface structures not found in the bulk. While growth of a new surface layer is initiated simultaneously (at the twin plane interface) on the {111}A and {111}B nanofacets, the step flow growth proceeds much faster on {111}A compared to {111}B leading to significant differences in roughness. Further, we observe that the atomic scale structures on the {111}B facet is different from its bulk counterpart and that shell growth on this facet occurs via steps perpendicular to the ⟨112⟩B-type directions.

Modulating the morphology and electrical properties of GaAs nanowires via catalyst stabilization by oxygen

Nowadays, III-V compound semiconductor nanowires (NWs) have attracted extensive research interest because of their high carrier mobility favorable for next-generation electronics. However, it is still a great challenge for the large-scale synthesis of III-V NWs with well-controlled and uniform morphology as well as reliable electrical properties, especially on the low-cost noncrystalline substrates for practical utilization. In this study, high-density GaAs NWs with lengths >10 μm and uniform diameter distribution (relative standard deviation σ ∼ 20%) have been successfully prepared by annealing the Au catalyst films (4-12 nm) in air right before GaAs NW growth, which is in distinct contrast to the ones of 2-3 μm length and widely distributed of σ ∼ 20-60% of the conventional NWs grown by the H2-annealed film. This air-annealing process is found to stabilize the Au nanoparticle seeds and to minimize Ostwald ripening during NW growth. Importantly, the obtained GaAs NWs exhibit uniform p-type conductivity when fabricated into NW-arrayed thin-film field-effect transistors (FETs). Moreover, they can be integrated with an n-type InP NW FET into effective complementary metal oxide semiconductor inverters, capable of working at low voltages of 0.5-1.5 V. All of these results explicitly demonstrate the promise of these NW morphology and electrical property controls through the catalyst engineering for next-generation electronics.

Complementary metal oxide semiconductor compatible silicon nanowires-on-a-chip: fabrication and preclinical validation for the detection of a cancer prognostic protein marker in serum

An integrated translational biosensing technology based on arrays of silicon nanowire field-effect transistors (SiNW FETs) is described and has been preclinically validated for the ultrasensitive detection of the cancer biomarker ALCAM in serum. High-quality SiNW arrays have been rationally designed toward their implementation as molecular biosensors. The FET sensing platform has been fabricated using a complementary metal oxide semiconductor (CMOS)-compatible process. Reliable and reproducible electrical performance has been demonstrated via electrical characterization using a custom-designed portable readout device. Using this platform, the cancer prognostic marker ALCAM could be detected in serum with a detection limit of 15.5 pg/mL. Importantly, the detection could be completed in less than 30 min and span a wide dynamic detection range (∼10(5)). The SiNW-on-a-chip biosensing technology paves the way to the translational clinical application of FET in the detection of cancer protein markers.

Mobility enhancement by Sb-mediated minimisation of stacking fault density in InAs nanowires grown on silicon

We report the growth of InAs(1-x)Sb(x) nanowires (0 ≤ x ≤ 0.15) grown by catalyst-free molecular beam epitaxy on silicon (111) substrates. We observed a sharp decrease of stacking fault density in the InAs(1-x)Sb(x) nanowire crystal structure with increasing antimony content. This decrease leads to a significant increase in the field-effect mobility, this being more than three times greater at room temperature for InAs0.85Sb0.15 nanowires than InAs nanowires.

Diameter-independent hole mobility in Ge/Si core/shell nanowire field effect transistors

Heterostructure engineering capability, especially in the radial direction, is a unique property of bottom-up nanowires (NWs) that makes them a serious candidate for high-performance field-effect transistors (FETs). In this Letter, we present a comprehensive study on size dependent carrier transport behaviors in vapor-liquid-solid grown Ge/Si core/shell NWFETs. Transconductance, subthreshold swing, and threshold voltage exhibit a linear increase with the NW diameter due to the increase of the transistor body size. Carrier confinement in this core/shell architecture is shown to maintain a diameter-independent hole mobility as opposed to surface-induced mobility degradation in homogeneous Ge NWs. The Si shell thickness also exhibits a slight effect on the hole mobility, while the most abrupt mobility transition is between structures with and without the Si shell. A hole mobility of 200 cm(2)/(V · s) is extracted from transistor performance for core/shell NWs with a diameter range of 15-50 nm and a 3 nm Si shell. The constant mobility enables a complete and unambiguous dependence of FET performance on NW diameter to be established and provides a caliper for performance comparisons between NWFETs and with other FET families.