Gate Dielectrics Integration for 2D Electronics: Challenges, Advances, and Outlook

Controllable Synthesis of Out-of-Plane Grown Bi2TeO5 with High-κ and Anisotropy for High-Performance Field-Effect Transistors

Two-dimensional (2D) van der Waals (vdW) dielectrics with high-κ and anisotropy are crucial for advanced field-effect transistors (FETs) and other anisotropic electronic devices. Here, we demonstrate a 2D vdW dielectric, Bi2TeO5, that uniquely combines high-κ with pronounced anisotropy. By adjusting the precursor mass during chemical vapor deposition, we can controllably synthesize Bi2TeO5 with orientations ranging from in-plane to out-of-plane. As a dielectric in MoS2 top-gate FETs, Bi2TeO5 achieves Ion/Ioff exceeding 107, a subthreshold swing of 65.2 mV dec-1, a small hysteresis of 15 mV, and ultralow leakage current density below 10-5 A cm-2, attributed to its large effective electron mass (m* = 27.4 m0). The FET shows stable performance over 1000 cycles. Additionally, Bi2TeO5 with in-plane anisotropy induces gate-tunable electrical anisotropic behaviors in monolayer MoS2 through interface coupling. Our findings introduce a high-performance dielectric for next-generation FETs and demonstrate its potential applications in anisotropic electronics.

MoS2 Transistors with 4 nm hBN Gate Dielectric and 0.46 V Threshold Voltage

The use of two-dimensional (2D) semiconducting materials (MoS2, WS2) as a channel in field-effect transistors may help extend Moore's law and produce devices beyond the complementary metal-oxide-semiconductor (CMOS) technology. Traditional dielectrics used in microelectronics (SiO2, HfO2, Al2O3) form a defective interface with the 2D semiconductor─because the latter does not have dangling bonds─leading to multiple device reliability issues and premature failure. Using 2D hexagonal boron nitride (hBN) as the gate dielectric sounds like a potential solution because it can form a clean van der Waals interface with the 2D semiconductor. However, its relative permittivity is only 3.6, which has raised concerns: it is believed that a MoS2 transistor with hBN gate dielectric cannot be switched ON without the apparition of gate leakage current. Here, we show that transistors with a Pt/4 nm-hBN/MoS2 vertical structure can exhibit ON/OFF current ratios above 105, low threshold voltage of 0.46 V, and low gate leakage current density (JG) of 10-4 A/cm2. Moreover, our Pt/hBN/MoS2 transistors show acceptable performance even after 1000 switching cycles: ON/OFF current ratio is above 104 and JG below 10-4 A/cm2. Our study indicates that hBN may be a suitable gate dielectric for some types of nanosized MoS2 transistors.

Influence Mechanism of Vertical Mirror Symmetry on Out-of-Plane Dielectric Properties in 2D Materials

In vertically integrated transistor structures, understanding the out-of-plane dielectric properties of 2D materials is crucial. We performed first-principles calculations to investigate the out-of-plane dielectric properties, including electronic and ionic polarization, of three types of 2D materials: transition metal dichalcogenides MX2 (M = Mo, W; X = S, Se, Te), transition metal halide nitrides MNX (M = Ti, Zr, Hf; X = Cl, Br), and MF4 (M = Sn, Pb). We identified a suppression mechanism for ionic polarization caused by vertical mirror symmetry, which becomes more pronounced with higher structural symmetry and atomic coordination. This mechanism ultimately reduces the out-of-plane ionic contribution of 2D MX2 to nearly zero. Using the classical spring oscillator model and second-order perturbation theory, we identified relevant physical quantities to specifically analyze the variation of the dielectric constant. This study provides a framework for analyzing 2D materials' dielectric properties and guides the design of novel dielectric materials.

High-Performance FETs with High-k STO by Optimized van der Waals Heterostructure Interface

The pursuit of suitable insulating layers and high-quality integration methods is important to further improve the performance of field-effect transistors (FETs). In this study, we employ transferable high-k oxide films as device gate dielectrics to fabricate high-quality optoelectronic devices by optimizing the interface between the dielectric material and the two-dimensional (2D) materials. Through meticulous refinement, a transferred film roughness of 269.27 pm was achieved, resulting in intact, crack-free SrTiO3 films. The molybdenum disulfide (MoS2) transistors exhibited remarkable characteristics, including a high on/off ratio (ION/IOFF) of 1 × 108, a subthreshold swing as low as 69.2 mV/dec, and a field-effect mobility reaching 230 cm2/(V·s). Additionally, the SrTiO3 films were combined with molybdenum telluride (MoTe2) to fabricate PN junctions capable of functioning as photodetectors at extremely low operating voltages (±2 V). The exceptional performance of both the MoS2 FETs and the MoTe2 PN junctions can be attributed to the optimized, high-quality dielectric/semiconductor heterojunction interface. This further demonstrates the versatility of the van der Waals integration method employed in this research.

Epitaxial Antiferroelectric Bi2O2S Films with Superior Photoresponse

Two-dimensional bismuth oxychalcogenide is a rising material system with superior electronic properties. However, a lack of high-quality synthesis impedes the exploration of fundamental understanding and practical applications. This work presents high-quality epitaxial Bi2O2S films on (LaAlO3)0.3(Sr2TaAlO6)0.7 with diverse properties by taking advantage of lattice compatibility. The atomically resolved sharp interface of Bi2O2S/(LaAlO3)0.3(Sr2TaAlO6)0.7 heteroepitaxy is observed with the verification of centrosymmetric breaking through microscopic evidence and macroscopic characterizations. Such an epitaxial feature of the Bi2O2S film provides an essential step for applications compared to those of chemically synthesized nanomaterials. The interior polarization and piezoelectricity can be investigated through atomic-scale observation and RhB degradation of BOS. Meanwhile, this synthesized system can achieve a strong photoresponse with an on/off ratio of ∼104 and a responsivity of ∼60 mA/W in the range of red light (620-750 nm). With these advantages, the demonstrated epitaxial Bi2O2S shows a huge potential for applications in high-performance optoelectronic devices.

Impact of Interface and Surface Oxide Defects on WS2 Electronic Properties from First Principles

The industrial-scale growth of dielectrics on top of a 2D material transistor channel without deterioration of its transport characteristics remains challenging today. Here, we investigate the origin of the performance degradation issue by constructing several atomistic interface models between a WS2 monolayer and an amorphous Al2O3 or HfO2 thin film. We then computed their properties using first-principles methods. We show that, while it is in principle possible to achieve a van der Waals interface between these materials, surface defects (e.g., undercoordinated metal atoms at the surface) are detrimental since they create localized states close to the bottom of the conduction band of WS2. Even in their absence, the inhomogeneity of the surface topology creates a nonuniform potential that is felt by charge carriers in WS2. While surface defects can potentially be kept under control with an appropriate oxide choice, the surface inhomogeneity appears to act as a bottleneck, limiting the performance of WS2 as a transistor channel and, in general, for all 2D materials.

Dielectric Integrations and Advanced Interface Engineering for 2D Field-Effect Transistors

As silicon-based transistors approach their physical limits, the challenge of further increasing chip integration intensifies. 2D semiconductors, with their atomically thin thickness, ultraflat surfaces, and van der Waals (vdW) integration capability, are seen as a key candidate for sub-1 nm nodes in the post-Moore era. However, the low dielectric integration quality, including discontinuity and substantial leakage currents due to the lack of nucleation sites during deposition, interfacial states causing serious charge scattering, uncontrolled threshold shifts, and bad uniformity from dielectric doping and damage, have become critical barriers to their real applications. This review focuses on this challenge and the possible solutions. The functions of dielectric materials in transistors and their criteria for 2D devices are first elucidated. The methods for high-quality dielectric integration with 2D channels, such as surface pretreatment, using 2D materials with native oxides, buffer layer insertion, vdW dielectric transfer, and new dielectric materials, are then reviewed. Additionally, the dielectric integration for advanced 3D integration of 2D materials is also discussed. Finally, this paper is concluded with a comparative summary and outlook, highlighting the importance of interfacial state control, dielectric integration for 2D p-type channels, and compatibility with silicon processes.

2D edge-seeded heteroepitaxy of ultrathin high-κ dielectric CaNb2O6 for 2D field-effect transistors

The experimental realization of single-crystalline high-κ dielectrics beyond two-dimensional (2D) layered materials is highly desirable for nanoscale field-effect transistors (FETs). However, the scalable synthesis of 2D nonlayered high-κ insulators is currently limited by uncontrolled isotropic three-dimensional growth, hampering the achievement of simultaneous high dielectric constants and low trap densities for small film thicknesses. Herein, we show a 2D edge-seeded heteroepitaxial strategy to synthesize ultrathin nonlayered 2D CaNb2O6 nanosheets by chemical vapor deposition, exhibiting high-crystalline quality, thickness-independent dielectric constant (~ 16) and breakdown field strength up to ~ 12 MV cm-1. The MoS2/CaNb2O6 FETs exhibit an on/off ratio of over ~ 107, a subthreshold swing down to 61 mV/dec and a negligible hysteresis. This work suggests a universal 2D edge-seeded heteroepitaxy and slow kinetic strategy for the scalable growth of 2D nonlayered dielectric and demonstrates 2D CaNb2O6 nanosheets as promising dielectrics for facilitating 2D electronic applications.

Dielectric Regulation in Quasi-vdW Europium Oxysulfur Compounds by Compositional Engineering for 2D Electronics

Advancing next-generation electronics necessitates precise control of dielectric properties in 2D materials. Here, the first synthesis of novel 2D quasi-van der Waals (vdW) europium oxysulfur (Eu2SOx) compounds, comprising hexagonal Eu₂SO₂ and tetragonal Eu₂SO₆ phases, with composition-tunable dielectric properties, is presented. Using a homodiffusive-controlled epitaxial growth method, materials are achieved with complementary characteristics: the hexagonal Eu₂SO₂ phase exhibits a high dielectric constant (≈30) paired with a moderate bandgap (≈4.56 eV), while the tetragonal Eu₂SO₆ phase offers a wider bandgap (≈5.62 eV) but a lower dielectric constant (≈20). The potential of these materials is demonstrated by integrating ultrathin Eu₂SO₂ nanoplates with molybdenum disulfide (MoS₂) field-effect transistors (FETs) via vdW forces. The resulting devices achieve a near-ideal Ion/Ioff ratio (≈10⁸), minimal hysteresis (≈5.3 mV), a low subthreshold slope (≈63.5 mV dec⁻¹), and ultralow leakage current (≈10⁻¹⁴ A). These results highlight the capacity of europium oxysulfur compounds to address the trade-off between dielectric constant and bandgap, offering tailored solutions for diverse 2D electronic applications. This work underscores the potential of composition engineering to expand the family of rare-earth oxysulfur compounds for nanoelectronics, paving the way for innovative gate dielectrics in next-generation devices.

Layered Deep-UV Optical Crystal KZn₂BO₃Br₂ as a High-κ Dielectric for 2D Electronic Devices

The development of dielectrics with atomic planes and van der Waals (vdW) interfaces is essential for enhancing the performance of 2D devices. However, vdW dielectrics often have smaller bandgaps compared to traditional 3D dielectrics, limiting their options. This study introduces AZBX (AZn₂BO₃X₂, where A = K or Rb, X = Cl or Br), a nonlinear deep-ultraviolet optical crystal, as a quasi-vdW layered dielectric ideal for 2D electronic devices. Focusing on KZBB, it's excellent dielectric properties, including a wide bandgap, high dielectric constant (high-κ), and smooth interfaces are demonstrated. When used as the top gate dielectric in a KZBB/MoS₂ field-effect transistor (FET) with MoS₂ channels and graphene contacts, the device exhibits outstanding performance, with a steep subthreshold swing (≈ 73 mV dec-1), high on/off ratio (≈ 10⁷), negligible hysteresis (0-8 mV), and stable, low leakage current (≈10⁻⁷ A cm- 2) before breakdown. This work expands the 2D material and dielectric landscape and highlights the strong potential of AZBX as high-performance dielectrics.

Capacitorless Dynamic Random Access Memory with 2D Transistors by One-Step Transfer of van der Waals Dielectrics and Electrodes

Dynamic random access memory (DRAM) has been a cornerstone of modern computing, but it faces challenges as technology scales down, particularly due to the mismatch between reduced storage capacitance and increasing OFF current. The capacitorless 2T0C DRAM architecture is recognized for its potential to offer superior area efficiency and reduced refresh rate requirements by eliminating the traditional capacitor. The exploration of two-dimensional (2D) materials further enhances scaling possibilities, though the absence of dangling bonds complicates the deposition of high-quality dielectrics. Here, we present a hexagonal boron nitride (h-BN)-assisted process for one-step transfer of van der Waals dielectrics and electrodes in 2D transistors with clean interfaces. The transferred aluminum oxide (Al2O3), formed by oxidizing aluminum (Al), exhibits exceptional flatness and uniformity, preserving the intrinsic properties of the 2D semiconductors without introducing doping effects. The MoS2 transistor exhibits an extremely low interface trap density of about 3 × 1011 cm-2 eV-1 and a leakage current density down to 10-7 A cm-2, which enables effective charge storage at the gate stack. This method allows for the simultaneous fabrication of two damage-free MoS2 transistors to form a capacitorless 2T0C DRAM cell, enhancing compatibility with 2D materials. The ultralow leakage current optimizes data retention and power efficiency. The fabricated 2T0C DRAM exhibits a rapid write speed of 20 ns, long data retention exceeding 1,000 s, and low energy consumption of approximately 0.2 fJ per write operation. Additionally, it demonstrates 3-bit storage capability and exceptional stability across numerous write/erase cycles.

A Single-Crystal Antimony Trioxide Dielectric for 2D Field-Effect Transistors

The remarkable potential of two-dimensional (2D) materials in sustaining Moore's law has sparked a research frenzy. Extensive efforts have been made in the research of utilizing 2D semiconductors as channel materials in field-effect transistors. However, the next generation of integrated devices requires the integration of gate dielectrics with wider bandgaps and higher dielectric constants. Here, insulating α-Sb2O3 single-crystal nanosheets are synthesized by one-step chemical vapor deposition method. Importantly, the α-Sb2O3 single-crystal dielectric exhibits a high dielectric constant of 11.8 and a wide bandgap of 3.78 eV. Besides, the atomically smooth interface between α-Sb2O3 and MoS2 enables the fabrication of dual-gated field-effect transistors with the top gate dielectric of α-Sb2O3 nanosheets. The field-effect transistors exhibit a switching ratio of exceeding 108, which achieves the manipulation of field-effect transistors by using 2D dielectric materials. These results hold significant implications for optimizing the performances of 2D devices and innovating microelectronics.

Janus Electronic Devices with Ultrathin High-κ Gate Dielectric Directly Integrated on 1T'-MoTe2

Integrating high-quality dielectrics with two-dimensional (2D) transition metal chalcogenides (TMDCs) is crucial for high-performance electronics. However, the lack of dangling bonds on 2D material surfaces complicates direct dielectric deposition. We propose using atomic layer deposition (ALD) to integrate ultrathin high-κ dielectric directly on 1T'-MoTe2 surfaces, facilitating the creation of high-performance back-gated field-effect transistors (FETs). Exploiting 1T'-MoTe2's natural oxidation in ambient conditions, we directly deposit dense and uniform HfO2 dielectric films below 5 nm, achieving an equivalent oxide thickness (EOT) of 0.97 nm. The resulting back-gate transistors, with a monolayer MoSSe on HfO2/1T'-MoTe2, show a current on/off ratio over 105 and operate at low voltages (<1 V), indicating high gating efficiency and a charge carrier mobility of 2.93 cm2V-1s-1. Additionally, we demonstrate a 6 × 5 bottom-gated array of MoSSe transistors using all-1T'-MoTe2 electrodes, achieving an 86.7% sample yield. Our approach also enables the creation of various integrated logic circuits such as inverters, NAND, and NOR gates. This research offers a feasible method for integrating high-κ dielectric films using industrially compatible ALD processes, providing excellent thickness control, uniformity, and scalability for 2D electronic devices.

Super High-k Unit-Cell-Thick α-CaCr2O4 Crystals

High-dielectric-constant (high-k) insulators are indispensable components to integrate semiconductors into metal-oxide-semiconductor field-effect transistors with sub-10 nm channel length, where the equivalent oxide thickness (EOT) of high-k insulator needs to be decreased to subnanometer scale. The traditional insulators, including Al2O3, SiO2, and HfO2, fit well with the existing silicon industry but suffer from serious degeneration of insulating properties, such as large leakage currents caused by high-density borders and interface traps, when their thicknesses are reduced to a few nanometers. Here, we synthesize a high-quality nonlayered ultrathin α-CaCr2O4 crystal down to unit-cell thickness (∼1.2 nm) by an elements slow-supply chemical vapor deposition (CVD) method. The unit-cell-thick α-CaCr2O4 crystals show a super high dielectric constant of 87.34, which is over 20 times higher than that of well-known layered insulator h-BN and corresponds to an EOT below 1 nm. Furthermore, it has a high breaking strength (39 GPa) and excellent stability. This strategy can also be used to fabricate other ultrathin ternary oxides, such as high-k ultrathin FeNb2O6 crystals, demonstrating the universality of the CVD method.

Low-Symmetry Van der Waals Dielectric GaInS3 Triggered 2D MoS2 Giant Anisotropy via Symmetry Engineering

Low-symmetry structures in van der Waals materials have facilitated the advancement of anisotropic electronic and optoelectronic devices. However, the intrinsic low symmetry structure exhibits a small adjustable anisotropy ratio (1-10), which hinders its further assembly and processing into high-performance devices. Here, a novel 2D anisotropic dielectric, GaInS3 (GIS), which induces isotropic MoS2 to exhibit significant anisotropic optical and electrical responses is demonstrated. With the excellent gate modulation ability of 2D GIS (dielectric constant k ∼12), MoS2 field effect transistor (FET) shows an adjustable conductance ratio from isotropic to anisotropic under dual-gate modulation, up to 106. Theoretical calculations indicate that anisotropy originates from lattice mismatch-induced charge density deformation at the interface. Moreover, the MoS2/GIS photodetector demonstrates high responsivity (≈4750 A W-1) and a large dichroic ratio (≈167). The anisotropic van der Waals dielectric GIS paves the way for the development of 2D transition metal dichalcogenides (TMDCs) in the fields of anisotropic photonics, electronics, and optoelectronics.

Reconfigurable Homojunction Phototransistor for Near-Zero Power Consumption Artificial Biomimetic Retina Function

Semiconductor photodetectors integrating preliminary signal-processing functions play a vital role in artificial biomimetic retina systems. Herein, we propose a tungsten diselenide (WSe2) phototransistor with a dual-layer gate dielectric and an asymmetric graphene insert structure. This phototransistor exhibits a bidirectional self-powered photocurrent by controlling the gate voltage via the formation of reconfigurable p+-p and n-p homojunctions in the channel from the asymmetric graphene insert. At the same time, the nonvolatile electron and hole stored in the dual-layer gate dielectric are generated using a temporary gate voltage, which can replace the gate voltage to regulate the channel charge. Moreover, the photocurrent shows a linear relation with the temporary programming gate voltage. The phototransistor exhibits a rectification ratio of >4 orders of magnitude without the gate voltage, indicating its significant capability to operate in a fully self-powered mode with near-zero power consumption. Based on the device characteristics, we successfully simulate the biological functions of the photoreceptor layer and bipolar cell layer in the retinal receptive field. The identification of the object motion direction in the receptive field can be realized by integrating three programmable devices on the chip. Furthermore, edge enhancement of the image is achieved by independently modulating the light response of each pixel in the sensor by varying the programming gate voltage. This study will promote the developing progress of future artificial biomimetic retina systems.

Synthesis, Modulation, and Application of Two-Dimensional TMD Heterostructures

Two-dimensional (2D) transition metal dichalcogenide (TMD) heterostructures have attracted a lot of attention due to their rich material diversity and stack geometry, precise controllability of structure and properties, and potential practical applications. These heterostructures not only overcome the inherent limitations of individual materials but also enable the realization of new properties through appropriate combinations, establishing a platform to explore new physical and chemical properties at micro-nano-pico scales. In this review, we systematically summarize the latest research progress in the synthesis, modulation, and application of 2D TMD heterostructures. We first introduce the latest techniques for fabricating 2D TMD heterostructures, examining the rationale, mechanisms, advantages, and disadvantages of each strategy. Furthermore, we emphasize the importance of characteristic modulation in 2D TMD heterostructures and discuss some approaches to achieve novel functionalities. Then, we summarize the representative applications of 2D TMD heterostructures. Finally, we highlight the challenges and future perspectives in the synthesis and device fabrication of 2D TMD heterostructures and provide some feasible solutions.

Atomic Precision Processing of Two-Dimensional Materials for Next-Generation Microelectronics

The growth of the information era economy is driving the pursuit of advanced materials for microelectronics, spurred by exploration into "Beyond CMOS" and "More than Moore" paradigms. Atomically thin 2D materials, such as transition metal dichalcogenides (TMDCs), show great potential for next-generation microelectronics due to their properties and defect engineering capabilities. This perspective delves into atomic precision processing (APP) techniques like atomic layer deposition (ALD), epitaxy, atomic layer etching (ALE), and atomic precision advanced manufacturing (APAM) for the fabrication and modification of 2D materials, essential for future semiconductor devices. Additive APP methods like ALD and epitaxy provide precise control over composition, crystallinity, and thickness at the atomic scale, facilitating high-performance device integration. Subtractive APP techniques, such as ALE, focus on atomic-scale etching control for 2D material functionality and manufacturing. In APAM, modification techniques aim at atomic-scale defect control, offering tailored device functions and improved performance. Achieving optimal performance and energy efficiency in 2D material-based microelectronics requires a comprehensive approach encompassing fundamental understanding, process modeling, and high-throughput metrology. The outlook for APP in 2D materials is promising, with ongoing developments poised to impact manufacturing and fundamental materials science. Integration with advanced metrology and codesign frameworks will accelerate the realization of next-generation microelectronics enabled by 2D materials.

Performance Limits and Advancements in Single 2D Transition Metal Dichalcogenide Transistor

Two-dimensional (2D) transition metal dichalcogenides (TMDs) allow for atomic-scale manipulation, challenging the conventional limitations of semiconductor materials. This capability may overcome the short-channel effect, sparking significant advancements in electronic devices that utilize 2D TMDs. Exploring the dimension and performance limits of transistors based on 2D TMDs has gained substantial importance. This review provides a comprehensive investigation into these limits of the single 2D-TMD transistor. It delves into the impacts of miniaturization, including the reduction of channel length, gate length, source/drain contact length, and dielectric thickness on transistor operation and performance. In addition, this review provides a detailed analysis of performance parameters such as source/drain contact resistance, subthreshold swing, hysteresis loop, carrier mobility, on/off ratio, and the development of p-type and single logic transistors. This review details the two logical expressions of the single 2D-TMD logic transistor, including current and voltage. It also emphasizes the role of 2D TMD-based transistors as memory devices, focusing on enhancing memory operation speed, endurance, data retention, and extinction ratio, as well as reducing energy consumption in memory devices functioning as artificial synapses. This review demonstrates the two calculating methods for dynamic energy consumption of 2D synaptic devices. This review not only summarizes the current state of the art in this field but also highlights potential future research directions and applications. It underscores the anticipated challenges, opportunities, and potential solutions in navigating the dimension and performance boundaries of 2D transistors.

Gamma-Irradiation-Induced Electrical Characteristic Variations in MoS2 Field-Effect Transistors with Buried Local Back-Gate Structure

The impact of radiation on MoS2-based devices is an important factor in the utilization of two-dimensional semiconductor-based technology in radiation-sensitive environments. In this study, the effects of gamma irradiation on the electrical variations in MoS2 field-effect transistors with buried local back-gate structures were investigated, and their related effects on Al2O3 gate dielectrics and MoS2/Al2O3 interfaces were also analyzed. The transfer and output characteristics were analyzed before and after irradiation. The current levels decreased by 15.7% under an exposure of 3 kGy. Additionally, positive shifts in the threshold voltages of 0.50, 0.99, and 1.15 V were observed under irradiations of 1, 2, and 3 kGy, respectively, compared to the non-irradiated devices. This behavior is attributable to the comprehensive effects of hole accumulation in the Al2O3 dielectric interface near the MoS2 side and the formation of electron trapping sites at the interface, which increased the electron tunneling at the MoS2 channel/dielectric interface.

Single-crystalline metal-oxide dielectrics for top-gate 2D transistors

Two-dimensional (2D) structures composed of atomically thin materials with high carrier mobility have been studied as candidates for future transistors1-4. However, owing to the unavailability of suitable high-quality dielectrics, 2D field-effect transistors (FETs) cannot attain the full theoretical potential and advantages despite their superior physical and electrical properties3,5,6. Here we demonstrate the fabrication of atomically thin single-crystalline Al2O3 (c-Al2O3) as a high-quality top-gate dielectric in 2D FETs. By using intercalative oxidation techniques, a stable, stoichiometric and atomically thin c-Al2O3 layer with a thickness of 1.25 nm is formed on the single-crystalline Al surface at room temperature. Owing to the favourable crystalline structure and well-defined interfaces, the gate leakage current, interface state density and dielectric strength of c-Al2O3 meet the International Roadmap for Devices and Systems requirements3,5,7. Through a one-step transfer process consisting of the source, drain, dielectric materials and gate, we achieve top-gate MoS2 FETs characterized by a steep subthreshold swing of 61 mV dec-1, high on/off current ratio of 108 and very small hysteresis of 10 mV. This technique and material demonstrate the possibility of producing high-quality single-crystalline oxides suitable for integration into fully scalable advanced 2D FETs, including negative capacitance transistors and spin transistors.

2D Reconfigurable van der Waals Heterojunction for Logic Gate Circuits and Wide-Spectrum Photodetectors via Sulfur Substitution and Band Matching

The attractive physical properties of two-dimensional (2D) semiconductors in group IVA-VIA have been fully revealed in recent years. Combining them with 2D ambipolar materials to construct van der Waals heterojunctions (vdWHs) can offer tremendous opportunities for designing multifunctional electronic and optoelectronic devices, such as logic switching circuits, half-wave rectifiers, and broad-spectrum photodetectors. Here, an optimized SnSe0.75S0.25 is grown to design a SnSe0.75S0.25/MoTe2 vdWH for logic operation and wide-spectrum photodetection. Benefiting from the excellent gate modulation under the appropriate sulfur substitution and type-II band alignment, the device exhibits reconfigurable antiambipolar and ambipolar transfer behaviors at positive and negative source-drain voltage (Vds), enabling stable XNOR logic operation. It also features a gate-modulated positive and negative rectifying behavior with rectification ratios of 265:1 and 1:196, confirming its potential as half-wave logic rectifiers. Besides, the device can respond from visible to infrared wavelength up to 1400 nm. Under 635 nm illumination, the maximum responsivity of 1.16 A/W and response time of 657/500 μs are achieved at the Vds of -2 V. Furthermore, due to the strong in-plane anisotropic structure of SnSe0.75S0.25-alloyed nanosheet and narrow bandgap of 2H-MoTe2, it shows a broadband polarization-sensitive function with impressive photocurrent anisotropic ratios of 15.6 (635 nm), 7.0 (808 nm), and 3.7 (1310 nm). The direction along the maximum photocurrent can be reconfigurable depending on the wavelengths. These results indicate that our designed alloyed SnSe0.75S0.25/MoTe2 vdWH has reconfigurable logic operation and broadband photodetection capabilities in 2D multifunctional integrated circuits.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5 V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60 mV dec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

Elastic Properties of Low-Dimensional Single-Crystalline Dielectric Oxides through Controlled Large-Area Wrinkle Generation

Freestanding single-crystalline SrTiO3 membranes, as high-κ dielectrics, hold significant promise as the gate dielectric in two-dimensional (2D) flexible electronics. Nevertheless, the mechanical properties of the SrTiO3 membranes, such as elasticity, remain a critical piece of the puzzle to adequately address the viability of their applications in flexible devices. Here, we report statistical analysis on plane-strain effective Young's modulus of large-area SrTiO3 membranes (5 × 5 mm2) over a series of thicknesses (from 6.5 to 32.2 nm), taking advantage of a highly efficient buckling-based method, which reveals its evident thickness-dependent behavior ranging from 46.01 to 227.17 GPa. Based on microscopic and theoretical results, we elucidate these thickness-dependent behaviors and statistical data deviation with a bilayer model, which consists of a surface layer and a bulk-like layer. The analytical results show that the ∼3.1 nm surface layer has a significant elastic softening compared to the bulk-like layer, while the extracted modulus of the bulk-like layer shows a variation of ∼40 GPa. This variation is considered as a combined contribution from oxygen deficiency presenting in SrTiO3 membranes, and the alignment between applied strain and the crystal orientation. Upon comparison of the extracted elastic properties and electrostatic control capability to those of other typical gate dielectrics, the superior performance of single-crystalline SrTiO3 membranes has been revealed in the context of flexible gate dielectrics, indicating the significant potential of their application in high-performance flexible 2D electronics.

High-κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low-Power Steep-Switching Computing Devices

Herein, a high-quality gate stack (native HfO2 formed on 2D HfSe2) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density (Dit ≈ 5 × 1010 cm-2 eV-1). The chemically converted HfO2 exhibits dielectric constant, κ ≈ 23, resulting in low gate leakage current (≈10-3 A cm-2) at equivalent oxide thickness ≈0.5 nm. Density functional calculations indicate that the atomistic mechanism for achieving a high-quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe2 layer without a substitution energy barrier, allowing layer-by-layer oxidation to proceed. The field-effect-transistor-fabricated HfO2/HfSe2 gate stack demonstrates an almost ideal subthreshold slope (SS) of ≈61 mV dec-1 (over four orders of IDS) at room temperature (300 K), along with a high Ion/Ioff ratio of ≈108 and a small hysteresis of ≈10 mV. Furthermore, by utilizing a device architecture with separately controlled HfO2/HfSe2 gate stack and channel structures, an impact ionization field-effect transistor is fabricated that exhibits n-type steep-switching characteristics with a SS value of 3.43 mV dec-1 at room temperature, overcoming the Boltzmann limit. These results provide a significant step toward the realization of post-Si semiconducting devices for future energy-efficient data-centric computing electronics.

Van der Waals Epitaxially Grown Molecular Crystal Dielectric Sb2O3 for 2D Electronics

Two-dimensional (2D) semiconducting materials have attracted significant interest as promising candidates for channel materials owing to their high mobility and gate tunability at atomic-layer thickness. However, the development of 2D electronics is impeded due to the difficulty in formation of high-quality dielectrics with a clean and nondestructive interface. Here, we report the direct van der Waals epitaxial growth of a molecular crystal dielectric, Sb2O3, on 2D materials by physical vapor deposition. The grown Sb2O3 nanosheets showed epitaxial relations of 0 and 180° with the 2D template, maintaining high crystallinity and an ultrasharp vdW interface with the 2D materials. As a result, the Sb2O3 nanosheets exhibited a high breakdown field of 18.6 MV/cm for 2L Sb2O3 with a thickness of 1.3 nm and a very low leakage current of 2.47 × 10-7 A/cm2 for 3L Sb2O3 with a thickness of 1.96 nm. We also observed two types of grain boundaries (GBs) with misorientation angles of 0 and 60°. The 0°-GB with a well-stitched boundary showed higher electrical and thermal stabilities than those of the 60°-GB with a disordered boundary. Our work demonstrates a method to epitaxially grow molecular crystal dielectrics on 2D materials without causing any damage, a requirement for high-performance 2D electronics.

Tailoring amorphous boron nitride for high-performance two-dimensional electronics

Two-dimensional (2D) materials have garnered significant attention in recent years due to their atomically thin structure and unique electronic and optoelectronic properties. To harness their full potential for applications in next-generation electronics and photonics, precise control over the dielectric environment surrounding the 2D material is critical. The lack of nucleation sites on 2D surfaces to form thin, uniform dielectric layers often leads to interfacial defects that degrade the device performance, posing a major roadblock in the realization of 2D-based devices. Here, we demonstrate a wafer-scale, low-temperature process (<250 °C) using atomic layer deposition (ALD) for the synthesis of uniform, conformal amorphous boron nitride (aBN) thin films. ALD deposition temperatures between 125 and 250 °C result in stoichiometric films with high oxidative stability, yielding a dielectric strength of 8.2 MV/cm. Utilizing a seed-free ALD approach, we form uniform aBN dielectric layers on 2D surfaces and fabricate multiple quantum well structures of aBN/MoS2 and aBN-encapsulated double-gated monolayer (ML) MoS2 field-effect transistors to evaluate the impact of aBN dielectric environment on MoS2 optoelectronic and electronic properties. Our work in scalable aBN dielectric integration paves a way towards realizing the theoretical performance of 2D materials for next-generation electronics.

Controllable Synthesis of Transferable Ultrathin Bi2Ge(Si)O5 Dielectric Alloys with Composition-Tunable High-κ Properties

Two-dimensional (2D) alloys hold great promise to serve as important components of 2D transistors, since their properties allow continuous regulation by varying their compositions. However, previous studies are mainly limited to the metallic/semiconducting ones as contact/channel materials, but very few are related to the insulating dielectrics. Here, we use a facile one-step chemical vapor deposition (CVD) method to synthesize ultrathin Bi2SixGe1-xO5 dielectric alloys, whose composition is tunable over the full range of x just by changing the relative ratios of the GeO2/SiO2 precursors. Moreover, their dielectric properties are highly composition-tunable, showing a record-high dielectric constant of >40 among CVD-grown 2D insulators. The vertically grown nature of Bi2GeO5 and Bi2SixGe1-xO5 enables polymer-free transfer and subsequent clean van der Waals integration as the high-κ encapsulation layer to enhance the mobility of 2D semiconductors. Besides, the MoS2 transistors using Bi2SixGe1-xO5 alloy as gate dielectrics exhibit a large Ion/Ioff (>108), ideal subthreshold swing of ∼61 mV/decade, and a small gate hysteresis (∼5 mV). Our work not only gives very few examples on controlled CVD growth of insulating dielectric alloys but also expands the family of 2D single-crystalline high-κ dielectrics.

RC-Effects on the Oxide of SOI MOSFET under Off-State TDDB Degradation: RF Characterization and Modeling

Based on S-parameter measurements, the effect of dynamic trapping and de-trapping of charge in the gate oxide, the increase of dielectric loss due to polarization, and the impact of leakage current on the small-signal input impedance at RF is analyzed and represented. This is achieved by systematically extracting the corresponding model parameters from single device measurements at different frequency ranges, and then the methodology is applied to analyze the evolution of these parameters when the device is submitted to non-conducting electrical stress. This approach not only allows to inspect the impact of effects not occurring under DC conditions, such as the current due to the time varying dielectric polarization, but also to clearly distinguish effects in accordance with the functional form of their contribution to the device's impedance. In fact, it is shown that minor changes in the model of the gate capacitance by including additional resistive and capacitive components allows for an excellent model-experiment correlation up to 30 GHz. Moreover, the accuracy of the correlation is shown to be maintained when applying the proposal to the device under different gate-to-source bias conditions and at several stages during off-state degradation.

Ultrathin Van der Waals Lanthanum Oxychloride Dielectric for 2D Field-Effect Transistors

Downsizing silicon-based transistors can result in lower power consumption, faster speeds, and greater computational capacity, although it is accompanied by the appearance of short-channel effects. The integration of high-mobility 2D semiconductor channels with ultrathin high dielectric constant (high-κ) dielectric in transistors is expected to suppress the effect. Nevertheless, the absence of a high-κ dielectric layer featuring an atomically smooth surface devoid of dangling bonds poses a significant obstacle in the advancement of 2D electronics. Here, ultrathin van der Waals (vdW) lanthanum oxychloride (LaOCl) dielectrics are successfully synthesized by precisely controlling the growth kinetics. These dielectrics demonstrate an impressive high-κ value of 10.8 and exhibit a remarkable breakdown field strength (Ebd ) exceeding 10 MV cm-1 . Remarkably, the conventional molybdenum disulfide (MoS2 ) field-effect transistor (FET) featuring a dielectric made of LaOCl showcases an almost negligible hysteresis when compared to FETs employing alternative gate dielectrics. This can be attributed to the flawlessly formed vdW interface and excellent compatibility established between LaOCl and MoS2 . These findings will motivate the further exploration of rare-earth oxychlorides and the development of more-than-Moore nanoelectronic devices.

p-Type Two-Dimensional Semiconductors: From Materials Preparation to Electronic Applications

Two-dimensional (2D) materials are regarded as promising candidates in many applications, including electronics and optoelectronics, because of their superior properties, including atomic-level thickness, tunable bandgaps, large specific surface area, and high carrier mobility. In order to bring 2D materials from the laboratory to industrialized applications, materials preparation is the first prerequisite. Compared to the n-type analogs, the family of p-type 2D semiconductors is relatively small, which limits the broad integration of 2D semiconductors in practical applications such as complementary logic circuits. So far, many efforts have been made in the preparation of p-type 2D semiconductors. In this review, we overview recent progresses achieved in the preparation of p-type 2D semiconductors and highlight some promising methods to realize their controllable preparation by following both the top-down and bottom-up strategies. Then, we summarize some significant application of p-type 2D semiconductors in electronic and optoelectronic devices and their superiorities. In end, we conclude the challenges existed in this field and propose the potential opportunities in aspects from the discovery of novel p-type 2D semiconductors, their controlled mass preparation, compatible engineering with silicon production line, high-κ dielectric materials, to integration and applications of p-type 2D semiconductors and their heterostructures in electronic and optoelectronic devices. Overall, we believe that this review will guide the design of preparation systems to fulfill the controllable growth of p-type 2D semiconductors with high quality and thus lay the foundations for their potential application in electronics and optoelectronics.

On the Working Mechanisms of Molecules-Based Van der Waals Dielectrics

Sb2 O3 molecules offer unprecedented opportunities for the integration of a van der Waals (vdW) dielectric and a 2D vdW semiconductor. However, the working mechanisms underlying molecules-based vdW dielectrics remain unclear. Here, the working mechanisms of Sb2 O3 and two Sb2 O3 -like molecules (As2 O3 and Bi2 O3 ) as dielectrics are systematically investigated by combining first-principles calculations and gate leakage current theories. It is revealed that molecules-based vdW dielectrics have a considerable advantage over conventional dielectric materials: defects hardly affect their insulating properties. This shows that it is unnecessary to synthesize high-quality crystals in practical applications, which has been a long-standing challenge for conventional dielectric materials. Further analysis reveals that a large thermionic-emission current renders Sb2 O3 difficult to simultaneously satisfy the requirements of dielectric layers in p-MOS and n-MOS, which hinders its application for complementary metal-oxide-semiconductor (CMOS) devices. Remarkably, it is found that As2 O3 can serve as a dielectric for both p-MOS and n-MOS. This work not only lays a theoretical foundation for the application of molecules-based vdW dielectrics, but also offers an unprecedentedly competitive dielectric (i.e., As2 O3 ) for 2D vdW semiconductors-based CMOS devices, thus having profound implications for future semiconductor industry.

Two-Dimensional Layered Materials Meet Perovskite Oxides: A Combination for High-Performance Electronic Devices

As the Si-based transistors scale down to atomic dimensions, the basic principle of current electronics, which heavily relies on the tunable charge degree of freedom, faces increasing challenges to meet the future requirements of speed, switching energy, heat dissipation, and packing density as well as functionalities. Heterogeneous integration, where dissimilar layers of materials and functionalities are unrestrictedly stacked at an atomic scale, is appealing for next-generation electronics, such as multifunctional, neuromorphic, spintronic, and ultralow-power devices, because it unlocks technologically useful interfaces of distinct functionalities. Recently, the combination of functional perovskite oxides and two-dimensional layered materials (2DLMs) led to unexpected functionalities and enhanced device performance. In this paper, we review the recent progress of the heterogeneous integration of perovskite oxides and 2DLMs from the perspectives of fabrication and interfacial properties, electronic applications, and challenges as well as outlooks. In particular, we focus on three types of attractive applications, namely field-effect transistors, memory, and neuromorphic electronics. The van der Waals integration approach is extendible to other oxides and 2DLMs, leading to almost unlimited combinations of oxides and 2DLMs and contributing to future high-performance electronic and spintronic devices.

Combination of Polymer Gate Dielectric and Two-Dimensional Semiconductor for Emerging Field-Effect Transistors

Two-dimensional (2D) materials are considered attractive semiconducting layers for emerging field-effect transistors owing to their unique electronic and optoelectronic properties. Polymers have been utilized in combination with 2D semiconductors as gate dielectric layers in field-effect transistors (FETs). Despite their distinctive advantages, the applicability of polymer gate dielectric materials for 2D semiconductor FETs has rarely been discussed in a comprehensive manner. Therefore, this paper reviews recent progress relating to 2D semiconductor FETs based on a wide range of polymeric gate dielectric materials, including (1) solution-based polymer dielectrics, (2) vacuum-deposited polymer dielectrics, (3) ferroelectric polymers, and (4) ion gels. Exploiting appropriate materials and corresponding processes, polymer gate dielectrics have enhanced the performance of 2D semiconductor FETs and enabled the development of versatile device structures in energy-efficient ways. Furthermore, FET-based functional electronic devices, such as flash memory devices, photodetectors, ferroelectric memory devices, and flexible electronics, are highlighted in this review. This paper also outlines challenges and opportunities in order to help develop high-performance FETs based on 2D semiconductors and polymer gate dielectrics and realize their practical applications.