Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control

High-Performance Carbon Nanotube-Based Transient Complementary Electronics

Transient electronics is an emerging class of electronic devices that can physically degrade or disintegrate after a stable period of service, showing a vast prospect in applications of "green" consumer electronics, hardware-secure devices, medical implants, etc. Complementary metal-oxide-semiconductor (CMOS) technology is dominant in integrated circuit design for its advantages of low static power consumption, high noise immunity, and simple design layout, which also work and are highly preferred for transient electronics. However, the performance of complementary transient electronics is severely restricted by the confined selection of transient materials and compatible fabrication strategies. Here, we report the realization of high-performance transient complementary electronics based on carbon nanotube thin films via a reliable electrostatic doping method. Under a low operating voltage of 2 V, on a 1.5 μm-thick water-soluble substrate made of poly(vinyl alcohol), the width-normalized on-state currents of the p-type and n-type transient thin-film transistors (TFTs) reach 4.5 and 4.7 μA/μm, and the width-normalized transconductances reach 2.8 and 3.7 μS/μm, respectively. Meanwhile, these TFTs show small subthreshold swings no more than 108 mV/dec and current on/off ratios above 10⁶ with good uniformity. Transient CMOS inverters, as basic circuit components, are demonstrated with a voltage gain of 24 and a high noise immunity of 67.4%. Finally, both the degradation of the active components and the disintegration of the functional system are continuously monitored with nontraceable remains after 10 and 5 h, respectively.

Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices

In this paper, we report the wafer-scale fabrication of carbon nanotube field-effect transistors (CNTFETs) with the dielectrophoresis (DEP) method. Semiconducting carbon nanotubes (CNTs) were positioned as the active channel material in the fabrication of carbon nanotube field-effect transistors (CNTFETs) with dielectrophoresis (DEP). The drain-source current (I_DS) was measured as a function of the drain-source voltage (V_DS) and gate-source voltage (V_GS) from each CNTFET on the fabricated wafer. The I_DS on/off ratio was derived for each CNTFET. It was found that 87% of the fabricated CNTFETs was functional, and that among the functional CNTFETs, 30% of the CNTFETs had an I_DS on/off ratio larger than 20 while 70% of the CNTFETs had an I_DS on/off ratio lower than 20. The highest I_DS on/off ratio was about 490. The DEP-based positioning of carbon nanotubes is simple and effective, and the DEP-based device fabrication steps are compatible with Si technology processes and could lead to the wafer-scale fabrication of CNT electronic devices.

Ambipolar Deep-Subthreshold Printed-Carbon-Nanotube Transistors for Ultralow-Voltage and Ultralow-Power Electronics

The development of ultralow-power and easy-to-fabricate electronics with potential for large-scale circuit integration (i.e., complementary or complementary-like) is an outstanding challenge for emerging off-the-grid applications, e.g., remote sensing, "place-and-forget", and the Internet of Things. Herein we address this challenge through the development of ambipolar transistors relying on solution-processed polymer-sorted semiconducting carbon nanotube networks (sc-SWCNTNs) operating in the deep-subthreshold regime. Application of self-assembled monolayers at the active channel interface enables the fine-tuning of sc-SWCNTN transistors toward well-balanced ambipolar deep-subthreshold characteristics. The significance of these features is assessed by exploring the applicability of such transistors to complementary-like integrated circuits, with respect to which the impact of the subthreshold slope and flatband voltage on voltage and power requirements is studied experimentally and theoretically. As demonstrated with inverter and NAND gates, the ambipolar deep-subthreshold sc-SWCNTN approach enables digital circuits with complementary-like operation and characteristics including wide noise margins and ultralow operational voltages (≤0.5 V), while exhibiting record-low power consumption (≤1 pW/μm). Among thin-film transistor technologies with minimal material complexity, our approach achieves the lowest energy and power dissipation figures reported to date, which are compatible with and highly attractive for emerging off-the-grid applications.

Energy-Efficient Tunneling Field-Effect Transistors for Low-Power Device Applications: Challenges and Opportunities

Conventional field-effect transistors (FETs) have long been considered a fundamental electronic component for a diverse range of devices. However, nanoelectronic circuits based on FETs are not energy efficient because they require a large supply voltage for switching applications. To reduce the supply voltage in standard FETs, which is hampered by the 60 mV/decade limit established by the subthreshold swing (SS), a new class of FETs have been designed, tunnel FETs (TFETs). A TFET utilizes charge-carrier transportation in device channels using quantum mechanical based band-to-band tunneling despite of conventional thermal injection. The TFETs fabricated with thin semiconducting film or nanowires can attain a 100-fold power drop compared to complementary metal-oxide-semiconductor (CMOS) transistors. As a result, the use of TFETs and CMOS technology together could ameliorate integrated circuits for low-power devices. The discovery of two-dimensional (2D) materials with a diverse range of electronic properties has also opened new gateways for condensed matter physics, nanotechnology, and material science, thus potentially improving TFET-based devices in terms of device design and performance. In this review, state-of-art TFET devices exhibiting different semiconducting channels and geometries are comprehensively reviewed followed by a brief discussion of the challenges that remain for the development of high-performance devices. Lastly, future prospects are presented for the improvement of device design and the working efficiency of TFETs.

Solution-Processing of High-Purity Semiconducting Single-Walled Carbon Nanotubes for Electronics Devices

High-purity semiconducting single-walled carbon nanotubes (s-SWCNTs) are of paramount significance for the construction of next-generation electronics. Until now, a number of elaborate sorting and purification techniques for s-SWCNTs have been developed, among which solution-based sorting methods show unique merits in the scale production, high purity, and large-area film formation. Here, the recent progress in the solution processing of s-SWCNTs and their application in electronic devices is systematically reviewed. First, the solution-based sorting and purification of s-SWCNTs are described, and particular attention is paid to the recent advance in the conjugated polymer-based sorting strategy. Subsequently, the solution-based deposition and morphology control of a s-SWCNT thin film on a surface are introduced, which focus on the strategies for network formation and alignment of SWCNTs. Then, the recent advances in electronic devices based on s-SWCNTs are reviewed with emphasis on nanoscale s-SWCNTs' high-performance integrated circuits and s-SWCNT-based thin-film transistors (TFT) array and circuits. Lastly, the existing challenges and development trends for the s-SWCNTs and electronic devices are briefly discussed. The aim is to provide some useful information and inspiration for the sorting and purification of s-SWCNTs, as well as the construction of electronic devices with s-SWCNTs.

Carbon Nanotube Complementary Gigahertz Integrated Circuits and Their Applications on Wireless Sensor Interface Systems

Along with ultralow-energy delay products and symmetric complementary polarities, carbon nanotube field-effect transistors (CNT FETs) are expected to be promising building blocks for energy-efficient computing technology. However, the work frequencies of the existing CNT-based complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are far below the requirement (850 MHz) in state-of-art wireless communication applications. In this work, we fabricated deep submicron CMOS FETs with considerably improved performance of n-type CNT FETs and hence significantly promoted the work frequency of CNT CMOS ICs to 1.98 GHz. Based on these high-speed and sensitive voltage-controlled oscillators, we then presented a wireless sensor interface circuit with working frequency up to 1.5 GHz spectrum. As a preliminary demonstration, an energy-efficient wireless temperature sensing interface system was realized combining a 150 mAh flexible Li-ion battery and a flexible antenna (center frequency of 915 MHz). In general, the CMOS-logic high-speed CNT ICs showed outstanding energy efficiency and thus may potentially advance the application of CNT-based electronics.

Tunable n-Type Doping of Carbon Nanotubes through Engineered Atomic Layer Deposition HfOX Films

Although digital systems fabricated from carbon-nanotube-based field-effect transistors (CNFETs) promise significant energy efficiency benefits, realizing these benefits requires a complementary CNFET technology, i.e., CNFET CMOS, comprising both PMOS and NMOS CNFETs. Furthermore, this CNFET CMOS process must be robust ( e.g., air-stable), tunable ( e.g., ability to control CNFET threshold voltages), and silicon CMOS compatible (to integrate within existing manufacturing facilities and process flows). Despite many efforts, such a silicon CMOS compatible CNT doping strategy for forming NMOS CNFETs does not exist. Techniques today are either not air-stable (using reactive low work function metals), not solid-state or silicon CMOS compatible (employing soluble molecular dopants in ionic solutions), or have not demonstrated precise control over the amount of doping (for setting threshold voltage,  V_T). Here, we demonstrate an electrostatic doping technique that meets all of these requirements. The key to our technique is leveraging atomic layer deposition (ALD) to encapsulate CNTs with nonstoichiometric oxides. We show that ALD allows for precise control of oxide stoichiometry, which translates to direct control of the amount of CNT doping. We experimentally demonstrate the ability to modulate the strength of the p-type conduction branch by >2500× (measured as the change in current at fixed bias), realize NMOS CNFETs with n-type conduction ∼500× stronger than p-type conduction (also measured by the relative current at fixed biases), and tune V_T over a ∼1.5 V range. Moreover, our technique is compatible with other doping schemes; as an illustration, we combine electrostatic doping and low work function contact engineering to achieve CNFET CMOS with symmetric NMOS and PMOS ( i.e., CNFET ON-current for NMOS and PMOS is within 6% of each other). Thus, this work realizes a solid-state, air-table, very large scale integration and silicon CMOS compatible doping strategy, enabling integration of CNFET CMOS within standard fabrication processes today.

Potential solution-induced HfAlO dielectrics and their applications in low-voltage-operating transistors and high-gain inverters

Recently, much attention has been paid to the investigation of solution-driven oxides for application in thin film transistors (TFTs). In current study, a fully solution-based method, using 2-methoxyethanol as solvent, has been adopted to prepare InZnO thin films and HfAlO _x gate dielectrics. Amorphous HfAlO _x thin films annealed at 600 °C have shown a high transparency (>85%), low leakage current density (6.9 × 10^-9 A cm^-2 at 2 MV cm^-1), and smooth surface. To verify the potential applications of HfAlO _x gate dielectrics in oxide-based TFTs, fully solution-induced InZnO/HfAlO _x TFTs have been integrated. Excellent electrical performance for InZnO/HfAlO _x TFTs annealed at 450 °C has been observed, including a low operating voltage of 3 V, a saturated mobility of 5.17 cm² V^-1 s^-1, a high I _on/I _off of ∼10⁶, a small subthreshold swing of 87 mV per decade, and a threshold voltage shift of 0.52 V under positive bias stress (PBS) for 7200 s, respectively. In addition, time dependent threshold voltage shift under PBS could be described by a stretched-exponential model, which can be due to charge trapping in the semiconductor/dielectric interface. Finally, to explore the possible application in logic operation, a resistor-loaded inverter based on InZnO/HfAlO _x TFTs has been built and excellent swing characteristic and well dynamic behavior have been obtained. Therefore, it can be concluded that fully solution-driven InZnO/HfAlO _x TFTs have demonstrated potential application in nontoxic, eco-friendly and low-power consumption oxide-based flexible electronics.

Printed Electronics Based on Inorganic Semiconductors: From Processes and Materials to Devices

Following the ever-expanding technological demands, printed electronics has shown palpable potential to create new and commercially viable technologies that will benefit from its unique characteristics, such as, large-area and wide range of substrate compatibility, conformability and low-cost. Through the last few decades, printed/solution-processed field-effect transistors (FETs) and circuits have witnessed immense research efforts, technological growth and increased commercial interests. Although printing of functional inks comprising organic semiconductors has already been initiated in early 1990s, gradually the attention, at least partially, has been shifted to various forms of inorganic semiconductors, starting from metal chalcogenides, oxides, carbon nanotubes and very recently to graphene and other 2D semiconductors. In this review, the entire domain of printable inorganic semiconductors is considered. In fact, thanks to the continuous development of materials/functional inks and novel design/printing strategies, the inorganic printed semiconductor-based circuits today have reached an operation frequency up to several hundreds of kilohertz with only a few nanosecond time delays at the individual FET/inverter levels; in this regard, often circuits based on hybrid material systems have been found to be advantageous. At the end, a comparison of relative successes of various printable inorganic semiconductor materials, the remaining challenges and the available future opportunities are summarized.

Fully solution-induced high performance indium oxide thin film transistors with ZrOx high-k gate dielectrics

Solution based deposition has been recently considered as a viable option for low-cost flexible electronics.

An All-Solution-Based Hybrid CMOS-Like Quantum Dot/Carbon Nanotube Inverter

The development of low-cost, flexible electronic devices is subordinated to the advancement in solution-based and low-temperature-processable semiconducting materials, such as colloidal quantum dots (QDs) and single-walled carbon nanotubes (SWCNTs). Here, excellent compatibility of QDs and SWCNTs as a complementary pair of semiconducting materials for fabrication of high-performance complementary metal-oxide-semiconductor (CMOS)-like inverters is demonstrated. The n-type field effect transistors (FETs) based on I^- capped PbS QDs (V_th = 0.2 V, on/off = 10⁵ , S_S-th = 114 mV dec^-1 , µ_e = 0.22 cm² V^-1 s^-1 ) and the p-type FETs with tailored parameters based on low-density random network of SWCNTs (V_th = -0.2 V, on/off > 10⁵ , S_S-th = 63 mV dec^-1 , µ_h = 0.04 cm² V^-1 s^-1 ) are integrated on the same substrate in order to obtain high-performance hybrid inverters. The inverters operate in the sub-1 V range (0.9 V) and have high gain (76 V/V), large maximum-equal-criteria noise margins (80%), and peak power consumption of 3 nW, in combination with low hysteresis (10 mV).

Solution-Processed Carbon Nanotube True Random Number Generator

With the growing adoption of interconnected electronic devices in consumer and industrial applications, there is an increasing demand for robust security protocols when transmitting and receiving sensitive data. Toward this end, hardware true random number generators (TRNGs), commonly used to create encryption keys, offer significant advantages over software pseudorandom number generators. However, the vast network of devices and sensors envisioned for the "Internet of Things" will require small, low-cost, and mechanically flexible TRNGs with low computational complexity. These rigorous constraints position solution-processed semiconducting single-walled carbon nanotubes (SWCNTs) as leading candidates for next-generation security devices. Here, we demonstrate the first TRNG using static random access memory (SRAM) cells based on solution-processed SWCNTs that digitize thermal noise to generate random bits. This bit generation strategy can be readily implemented in hardware with minimal transistor and computational overhead, resulting in an output stream that passes standardized statistical tests for randomness. By using solution-processed semiconducting SWCNTs in a low-power, complementary architecture to achieve TRNG, we demonstrate a promising approach for improving the security of printable and flexible electronics.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Selective Conversion from p-Type to n-Type of Printed Bottom-Gate Carbon Nanotube Thin-Film Transistors and Application in Complementary Metal-Oxide-Semiconductor Inverters

The fabrication of printed high-performance and environmentally stable n-type single-walled carbon nanotube (SWCNT) transistors and their integration into complementary (i.e., complementary metal-oxide-semiconductor, CMOS) circuits are widely recognized as key to achieving the full potential of carbon nanotube electronics. Here, we report a simple, efficient, and robust method to convert the polarity of SWCNT thin-film transistors (TFTs) using cheap and readily available ethanolamine as an electron doping agent. Printed p-type bottom-gate SWCNT TFTs can be selectively converted into n-type by deposition of ethanolamine inks on the transistor active region via aerosol jet printing. Resulted n-type TFTs show excellent electrical properties with an on/off ratio of 10⁶, effective mobility up to 30 cm² V^-1 s^-1, small hysteresis, and small subthreshold swing (90-140 mV dec^-1), which are superior compared to the original p-type SWCNT devices. The n-type SWCNT TFTs also show good stability in air, and any deterioration of performance due to shelf storage can be fully recovered by a short low-temperature annealing. The easy polarity conversion process allows construction of CMOS circuitry. As an example, CMOS inverters were fabricated using printed p-type and n-type TFTs and exhibited a large noise margin (50 and 103% of 1/2 V_dd = 1 V) and a voltage gain as high as 30 (at V_dd = 1 V). Additionally, the CMOS inverters show full rail-to-rail output voltage swing and low power dissipation (0.1 μW at V_dd = 1 V). The new method paves the way to construct fully functional complex CMOS circuitry by printed TFTs.

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design.

Direct transfer of graphene and application in low-voltage hybrid transistors

Scotch tape assisted direct transfer of graphene is presented. Transferred graphene can act as a carrier transport layer in In₂O₃/graphene/ZrO₂transistor.

Assembly and Electronic Applications of Colloidal Nanomaterials

Artificial solids and thin films assembled from colloidal nanomaterials give rise to versatile properties that can be exploited in a range of technologies. In particular, solution-based processes allow for the large-scale and low-cost production of nanoelectronics on rigid or mechanically flexible substrates. To achieve this goal, several processing steps require careful consideration, including nanomaterial synthesis or exfoliation, purification, separation, assembly, hybrid integration, and device testing. Using a ubiquitous electronic device - the field-effect transistor - as a platform, colloidal nanomaterials in three electronic material categories are reviewed systematically: semiconductors, conductors, and dielectrics. The resulting comparative analysis reveals promising opportunities and remaining challenges for colloidal nanomaterials in electronic applications, thereby providing a roadmap for future research and development.

Fully Printed and Encapsulated SWCNT-Based Thin Film Transistors via a Combination of R2R Gravure and Inkjet Printing

Fully printed thin film transistors (TFT) based on poly(9,9-di-n-dodecylfluorene) (PFDD) wrapped semiconducting single walled carbon nanotube (SWCNT) channels are fabricated by a practical route that combines roll-to-roll (R2R) gravure and ink jet printing. SWCNT network density is easily controlled via ink formulation (concentration and polymer:CNT ratio) and jetting conditions (droplet size, drop spacing, and number of printed layers). Optimum inkjet printing conditions are established on Si/SiO₂ in which an ink consisting of 6:1 PFDD:SWCNT ratio with 50 mg L^-1 SWCNT concentration printed at a drop spacing of 20 μm results in TFTs with mobilities of ∼25 cm² V^-1 s^-1 and on-/off-current ratios > 10⁵. These conditions yield excellent network uniformity and are used in a fully additive process to fabricate fully printed TFTs on PET substrates with mobility values > 5 cm² V^-1 s^-1 (R2R printed gate electrode and dielectric; inkjet printed channel and source/drain electrodes). An inkjet printed encapsulation layer completes the TFT process (fabricated in bottom gate, top contact TFT configuration) and provides mobilities > 1 cm² V^-1 s^-1 with good operational stability, based on the performance of an inverter circuit. An array of 20 TFTs shows that most have less than 10% variability in terms of threshold voltage, transconductance, on-current, and subthreshold swing.

Flexible CMOS-Like Circuits Based on Printed P-Type and N-Type Carbon Nanotube Thin-Film Transistors

P-type and n-type top-gate carbon nanotube thin-film transistors (TFTs) can be selectively and simultaneously fabricated on the same polyethylene terephthalate (PET) substrate by tuning the types of polymer-sorted semiconducting single-walled carbon nanotube (sc-SWCNT) inks, along with low temperature growth of HfO₂ thin films as shared dielectric layers. Both the p-type and n-type TFTs show good electrical properties with on/off ratio of ≈10⁵ , mobility of ≈15 cm² V^-1 s^-1 , and small hysteresis. Complementary metal oxide semiconductor (CMOS)-like logic gates and circuits based on as-prepared p-type and n-type TFTs have been achieved. Flexible CMOS-like inverters exhibit large noise margin of 84% at low voltage (1/2 V_dd = 1.5 V) and maximum voltage gain of 30 at V_dd of 1.5 V and low power consumption of 0.1 μW. Both of the noise margin and voltage gain are one of the best values reported for flexible CMOS-like inverters at V_dd less than 2 V. The printed CMOS-like inverters work well at 10 kHz with 2% voltage loss and delay time of ≈15 μs. A 3-stage ring oscillator has also been demonstrated on PET substrates and the oscillation frequency of 3.3 kHz at V_dd of 1 V is achieved.

High-Performance Inkjet-Printed Indium-Gallium-Zinc-Oxide Transistors Enabled by Embedded, Chemically Stable Graphene Electrodes

Recent developments in solution-processed amorphous oxide semiconductors have established indium-gallium-zinc-oxide (IGZO) as a promising candidate for printed electronics. A key challenge for this vision is the integration of IGZO thin-film transistor (TFT) channels with compatible source/drain electrodes using low-temperature, solution-phase patterning methods. Here we demonstrate the suitability of inkjet-printed graphene electrodes for this purpose. In contrast to common inkjet-printed silver-based conductive inks, graphene provides a chemically stable electrode-channel interface. Furthermore, by embedding the graphene electrode between two consecutive IGZO printing passes, high-performance IGZO TFTs are achieved with an electron mobility of ∼6 cm(2)/V·s and current on/off ratio of ∼10(5). The resulting printed devices exhibit robust stability to aging in ambient as well as excellent resilience to thermal stress, thereby offering a promising platform for future printed electronics applications.

Controlled n-Type Doping of Carbon Nanotube Transistors by an Organorhodium Dimer

Single-walled carbon nanotube (SWCNT) transistors are among the most developed nanoelectronic devices for high-performance computing applications. While p-type SWCNT transistors are easily achieved through adventitious adsorption of atmospheric oxygen, n-type SWCNT transistors require extrinsic doping schemes. Existing n-type doping strategies for SWCNT transistors suffer from one or more issues including environmental instability, limited carrier concentration modulation, undesirable threshold voltage control, and/or poor morphology. In particular, commonly employed benzyl viologen n-type doping layers possess large thicknesses, which preclude top-gate transistor designs that underlie high-density integrated circuit layouts. To overcome these limitations, we report here the controlled n-type doping of SWCNT thin-film transistors with a solution-processed pentamethylrhodocene dimer. The charge transport properties of organorhodium-treated SWCNT thin films show consistent n-type behavior when characterized in both Hall effect and thin-film transistor geometries. Due to the molecular-scale thickness of the organorhodium adlayer, large-area arrays of top-gated, n-type SWCNT transistors are fabricated with high yield. This work will thus facilitate ongoing efforts to realize high-density SWCNT integrated circuits.

Chemically Tailoring Semiconducting Two-Dimensional Transition Metal Dichalcogenides and Black Phosphorus

Two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDCs) and black phosphorus (BP) have beneficial electronic, optical, and physical properties at the few-layer limit. As atomically thin materials, 2D TMDCs and BP are highly sensitive to their environment and chemical modification, resulting in a strong dependence of their properties on substrate effects, intrinsic defects, and extrinsic adsorbates. Furthermore, the integration of 2D semiconductors into electronic and optoelectronic devices introduces unique challenges at metal-semiconductor and dielectric-semiconductor interfaces. Here, we review emerging efforts to understand and exploit chemical effects to influence the properties of 2D TMDCs and BP. In some cases, surface chemistry leads to significant degradation, thus necessitating the development of robust passivation schemes. On the other hand, appropriately designed chemical modification can be used to beneficially tailor electronic properties, such as controlling doping levels and charge carrier concentrations. Overall, chemical methods allow substantial tunability of the properties of 2D TMDCs and BP, thereby enabling significant future opportunities to optimize performance for device applications.

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect.

Printed thin film transistors and CMOS inverters based on semiconducting carbon nanotube ink purified by a nonlinear conjugated copolymer

Two innovative research studies are reported in this paper. One is the sorting of semiconducting carbon nanotubes and ink formulation by a novel semiconductor copolymer and second is the development of CMOS inverters using not the p-type and n-type transistors but a printed p-type transistor and a printed ambipolar transistor. A new semiconducting copolymer (named P-DPPb5T) was designed and synthesized with a special nonlinear structure and more condensed conjugation surfaces, which can separate large diameter semiconducting single-walled carbon nanotubes (sc-SWCNTs) from arc discharge SWCNTs according to their chiralities with high selectivity. With the sorted sc-SWCNTs ink, thin film transistors (TFTs) have been fabricated by aerosol jet printing. The TFTs displayed good uniformity, low operating voltage (±2 V) and subthreshold swing (SS) (122-161 mV dec(-1)), high effective mobility (up to 17.6-37.7 cm(2) V(-1) s(-1)) and high on/off ratio (10(4)-10(7)). With the printed TFTs, a CMOS inverter was constructed, which is based on the p-type TFT and ambipolar TFT instead of the conventional p-type and n-type TFTs. Compared with other recently reported inverters fabricated by printing, the printed CMOS inverters demonstrated a better noise margin (74% 1/2 Vdd) and was hysteresis free. The inverter has a voltage gain of up to 16 at an applied voltage of only 1 V and low static power consumption.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

Layer-by-Layer Assembled 2D Montmorillonite Dielectrics for Solution-Processed Electronics

Layer-by-layer assembled 2D montmorillonite nanosheets are shown to be high-performance, solution-processed dielectrics. These scalable and spatially uniform sub-10 nm thick dielectrics yield high areal capacitances of ≈600 nF cm(-2) and low leakage currents down to 6 × 10(-9) A cm(-2) that enable low voltage operation of p-type semiconducting single-walled carbon nanotube and n-type indium gallium zinc oxide field-effect transistors.

Inkjet Printed Circuits on Flexible and Rigid Substrates Based on Ambipolar Carbon Nanotubes with High Operational Stability

Inkjet printed ambipolar transistors and circuits with high operational stability are demonstrated on flexible and rigid substrates employing semiconducting single-walled carbon nanotubes (SWCNTs). All patterns, which include electrodes, semiconductors, and vias, are realized by inkjet printing without the use of rigid physical masks and photolithography. An Al2O3 layer deposited on devices by atomic layer deposition (ALD) transforms p-type SWCNT thin-film transistors (TFTs) into ambipolar SWCNT TFTs and encapsulates them effectively. The ambipolar SWCNT TFTs have balanced electron and hole mobilities, which facilitates their use in multicomponent circuits. For example, a variety of logic gates and ring oscillators are demonstrated based on the ambipolar TFTs. The three-stage ring oscillator operates continuously for longer than 80 h under ambient conditions with only slight deviations in oscillation frequency. The successful demonstration of ambipolar devices by inkjet printing will enable a new class of circuits that utilize n-channel, p-channel, and ambipolar circuit components.

Short Channel Field-Effect-Transistors with Inkjet-Printed Semiconducting Carbon Nanotubes

Short channel field-effect-transistors with inkjet-printed semiconducting carbon nanotubes are fabricated using a novel strategy to minimize material consumption, confining the inkjet droplet into the active channel area. This fabrication approach is compatible with roll-to-roll processing and enables the formation of high-performance short channel device arrays based on inkjet printing.

Solution-processed carbon nanotube thin-film complementary static random access memory

Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

Voltage-Controlled Ring Oscillators Based on Inkjet Printed Carbon Nanotubes and Zinc Tin Oxide

A voltage-controlled ring oscillator is implemented with double-gate complementary transistors where both the n- and p-channel semiconductors are deposited by inkjet printing. Top gates added to transistors in conventional ring oscillator circuits control not only threshold voltages of the constituent transistors but also the oscillation frequencies of the ring oscillators. The oscillation frequency increases or decreases linearly with applied top gate potential. The field-effect transistor materials system that yields such linear behavior has not been previously reported. In this work, we demonstrate details of a material system (gate insulator, p- and n-channel semiconductors) that results in very linear frequency changes with control gate potential. Our use of a double layer top dielectric consisting of a combination of solution processed P(VDF-TrFE) and Al2O3 deposited by atomic layer deposition leads to low operating voltages and near-optimal device characteristics from a circuit standpoint. Such functional blocks will enable the realization of printed voltage-controlled oscillator-based analog-to-digital converters.

Emerging Carbon and Post-Carbon Nanomaterial Inks for Printed Electronics

Carbon and post-carbon nanomaterials present desirable electrical, optical, chemical, and mechanical attributes for printed electronics, offering low-cost, large-area functionality on flexible substrates. In this Perspective, recent developments in carbon nanomaterial inks are highlighted. Monodisperse semiconducting single-walled carbon nanotubes compatible with inkjet and aerosol jet printing are ideal channels for thin-film transistors, while inkjet, gravure, and screen-printable graphene-based inks are better-suited for electrodes and interconnects. Despite the high performance achieved in prototype devices, additional effort is required to address materials integration issues encountered in more complex systems. In this regard, post-carbon nanomaterial inks (e.g., electrically insulating boron nitride and optically active transition-metal dichalcogenides) present promising opportunities. Finally, emerging work to extend these nanomaterial inks to three-dimensional printing provides a path toward nonplanar devices. Overall, the superlative properties of these materials, coupled with versatile assembly by printing techniques, offer a powerful platform for next-generation printed electronics.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

High-gain subnanowatt power consumption hybrid complementary logic inverter with WSe2 nanosheet and ZnO nanowire transistors on glass

A 1D-2D hybrid complementary logic inverter comprising of ZnO nanowire and WSe2 nanosheet field-effect transistors (FETs) is fabricated on glass, which shows excellent static and dynamic electrical performances with a voltage gain of ≈60, sub-nanowatt power consumption, and at least 1 kHz inverting speed.

Flexible logic circuits based on top-gate thin film transistors with printed semiconductor carbon nanotubes and top electrodes

In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfO(x) thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ∼ 46.2 cm(2) V(-1) s(-1), 10(5) and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 μs. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates.

Trap-state-dominated suppression of electron conduction in carbon nanotube thin-film transistors

The often observed p-type conduction of single carbon nanotube field-effect transistors is usually attributed to the Schottky barriers at the metal contacts induced by the work function differences or by the doping effect of the oxygen adsorption when carbon nanotubes are exposed to air, which cause the asymmetry between electron and hole injections. However, for carbon nanotube thin-film transistors, our contrast experiments between oxygen doping and electrostatic doping demonstrate that the doping-generated transport barriers do not introduce any observable suppression of electron conduction, which is further evidenced by the perfect linear behavior of transfer characteristics with the channel length scaling. On the basis of the above observation, we conclude that the environmental adsorbates work by more than simply shifting the Fermi level of the CNTs; more importantly, these adsorbates cause a poor gate modulation efficiency of electron conduction due to the relatively large trap state density near the conduction band edge of the carbon nanotubes, for which we further propose quantitatively that the adsorbed oxygen-water redox couple is responsible.

Highly stable carbon nanotube top-gate transistors with tunable threshold voltage

Carbon-nanotube top-gate transistors with fluorinated dielectrics are presented. With PTrFE as the dielectric, the devices have absent or small hysteresis at different sweep rates and excellent bias-stress stability under ambient conditions. Ambipolar single-walled carbon nanotube (SWNT) transistors are observed when P(VDF-TrFE-CTFE) is utilized as a topgate dielectric. Furthermore, continuous tuning of the threshold voltages of both unipolar and ambipolar SWNT thin-film transistors (TFTs) is demonstrated for the first time.

Self-aligned Cu etch mask for individually addressable metallic and semiconducting carbon nanotubes

Two means to achieve high yield of individually addressable single-walled carbon nanotubes (CNTs) are developed and examined. The first approach matches the effective channel width and the density of horizontally aligned CNTs. This method can provide single CNT devices and also allows control over the average number of CNTs per channel. The second and a more deterministic approach uses self-aligned Cu-filled trenches formed in a photoresist (after Joule heating of the underlying CNT) to protect and obtain a large number of single CNT devices. Unlike electrical breakdown methods, which preserve the least conducting CNT and can leave behind CNT fragments, our approach allows the selection of the single most conducting metallic CNT from an array of as-grown CNTs with average resistance ∼14 times lower than that of as-fabricated single metallic CNTs. This method can also be used to select the best semiconducting CNT from an array and yields, on average, devices that are 15 times more conductive with 40 times higher ON/OFF ratio than those selected through electrical breakdown alone.

High-speed, inkjet-printed carbon nanotube/zinc tin oxide hybrid complementary ring oscillators

The materials combination of inkjet-printed single-walled carbon nanotubes (SWCNTs) and zinc tin oxide (ZTO) is very promising for large-area thin-film electronics. We compare the characteristics of conventional complementary inverters and ring oscillators measured in air (with SWCNT p-channel field effect transistors (FETs) and ZTO n-channel FETs) with those of ambipolar inverters and ring oscillators comprised of bilayer SWCNT/ZTO FETs. This is the first such comparison between the performance characteristics of ambipolar and conventional inverters and ring oscillators. The measured signal delay per stage of 140 ns for complementary ring oscillators is the fastest for any ring oscillator circuit with printed semiconductors to date.

Surface selective one-step fabrication of carbon nanotube thin films with high density

Thin films of carbon nanotubes (CNTs) are fabricated from solution using a one-step directed assembly strategy. Very high surface selectivity and exceptionally high CNT densities can be observed in small features with complex shapes. This directed assembly technique makes use of minimum amounts of CNTs and low toxicity solvents, and can be applied to metallic, semiconducting and mixed CNTs for fabrication of thin films over macroscopic areas. The thin films obtained with this approach are used for thin-film transistor (TFT) fabrication, and their electrical characterization is described.

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at V(DD) = 80 V (70% of 1/2V(DD)) and a gain of 85. Additionally, robust SWNT complementary metal-oxide-semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate.

Emerging device applications for semiconducting two-dimensional transition metal dichalcogenides

With advances in exfoliation and synthetic techniques, atomically thin films of semiconducting transition metal dichalcogenides have recently been isolated and characterized. Their two-dimensional structure, coupled with a direct band gap in the visible portion of the electromagnetic spectrum, suggests suitability for digital electronics and optoelectronics. Toward that end, several classes of high-performance devices have been reported along with significant progress in understanding their physical properties. Here, we present a review of the architecture, operating principles, and physics of electronic and optoelectronic devices based on ultrathin transition metal dichalcogenide semiconductors. By critically assessing and comparing the performance of these devices with competing technologies, the merits and shortcomings of this emerging class of electronic materials are identified, thereby providing a roadmap for future development.

Utilizing carbon nanotube electrodes to improve charge injection and transport in bis(trifluoromethyl)-dimethyl-rubrene ambipolar single crystal transistors

We have examined the significant enhancement of ambipolar charge injection and transport properties of bottom-contact single crystal field-effect transistors (SC-FETs) based on a new rubrene derivative, bis(trifluoromethyl)-dimethyl-rubrene (fm-rubrene), by employing carbon nanotube (CNT) electrodes. The fundamental challenge associated with fm-rubrene crystals is their deep-lying HOMO and LUMO energy levels, resulting in inefficient hole injection and suboptimal electron injection from conventional Au electrodes due to large Schottky barriers. Applying thin layers of CNT network at the charge injection interface of fm-rubrene crystals substantially reduces the contact resistance for both holes and electrons; consequently, benchmark ambipolar mobilities have been achieved, reaching 4.8 cm(2) V(-1) s(-1) for hole transport and 4.2 cm(2) V(-1) s(-1) for electron transport. We find that such improved injection efficiency in fm-rubrene is beneficial for ultimately unveiling its intrinsic charge transport properties so as to exceed those of its parent molecule, rubrene, in the current device architecture. Our studies suggest that CNT electrodes may provide a universal approach to ameliorate the charge injection obstacles in organic electronic devices regardless of charge carrier type, likely due to the electric field enhancement along the nanotube located at the crystal/electrode interface.