Three-dimensional integration of nanotechnologies for computing and data storage on a single chip

Monolithic three-dimensional tier-by-tier integration via van der Waals lamination

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

Bio-Inspired Sensory Receptors for Artificial-Intelligence Perception

In the era of artificial intelligence (AI), there is a growing interest in replicating human sensory perception. Selective and sensitive bio-inspired sensory receptors with synaptic plasticity have recently gained significant attention in developing energy-efficient AI perception. Various bio-inspired sensory receptors and their applications in AI perception are reviewed here. The critical challenges for the future development of bio-inspired sensory receptors are outlined, emphasizing the need for innovative solutions to overcome hurdles in sensor design, integration, and scalability. AI perception can revolutionize various fields, including human-machine interaction, autonomous systems, medical diagnostics, environmental monitoring, industrial optimization, and assistive technologies. As advancements in bio-inspired sensing continue to accelerate, the promise of creating more intelligent and adaptive AI systems becomes increasingly attainable, marking a significant step forward in the evolution of human-like sensory perception.

Monolithic 3D Integration of Analog RRAM-Based Computing-in-Memory and Sensor for Energy-Efficient Near-Sensor Computing

In the era of the Internet of Things, vast amounts of data generated at sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits serves as the control logic and peripheral circuits. The 2nd layer comprises a 1 k-bit one-transistor-one-resistor (1T1R) array with InGaZnOx field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprises multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer are comprehensively verified. Furthermore, NSC is implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5× lower energy consumption and 1.91× faster computing speed compared to its 2D counterpart.

Self-healing flexible strain sensor fabricated through 3D printing template sacrifice for motion monitoring with enhanced healing and mechanical performance

With the advancements in flexible materials and information technology, flexible sensors are becoming increasingly pervasive in various aspects of life and production. They hold immense potential for further development in areas such as motion detection, electronic skin, soft robots, and wearable devices. Aminopropyl-terminated polydimethylsiloxane (PDMS) was used as the raw material, while a diisocyanate reagent served as the cross-linking agent for the polymerization reaction, which involved the introduction of ureido groups, containing N-H and C=O bonds, into the long siloxane chain. The dynamic hydrogen bonding between the clusters completes the self-healing of the material. Using 1-[3-(trimethoxysilyl)propyl]urea as a grafting agent, the urea groups are introduced into graphene oxide and carbon nanotubes (CNTs) as conductive fillers. Subsequently, a flexible polymer is used as the substrate to prepare conductive flexible self-healing composites. By controlling the amount of conductive fillers, flexible strain materials with varying sensitivities are obtained. Design the structure of the flexible strain sensor using three-dimensional (3D) modeling software with deposition printing method.

Large-range two-dimensional sub-nano-misalignment sensing for lithography with a piecewise frequency regression network

Circular gratings have been traditionally used as coarse alignment markers rather than fine ones for carrying out two-dimensional (2D) large-range misalignment measurements. This is primarily due to its complex phase distribution, which renders the extraction of information from high-precision alignment challenging using conventional frequency filtering methods. Along these lines, in this work, a novel, to the best of our knowledge, convolutional regression filter capable of achieving a 2D misalignment measurement with an impressive accuracy of 0.82 nm across a 3 mm range was introduced. Importantly, the proposed approach exhibited robustness against system errors and noise. It is anticipated that this strategy will provide an effective solution for similar misalignment sensing applications and hold promise for addressing future challenges in these fields.

Hardware implementation of memristor-based artificial neural networks

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

The Roadmap of 2D Materials and Devices Toward Chips

Due to the constraints imposed by physical effects and performance degradation, silicon-based chip technology is facing certain limitations in sustaining the advancement of Moore's law. Two-dimensional (2D) materials have emerged as highly promising candidates for the post-Moore era, offering significant potential in domains such as integrated circuits and next-generation computing. Here, in this review, the progress of 2D semiconductors in process engineering and various electronic applications are summarized. A careful introduction of material synthesis, transistor engineering focused on device configuration, dielectric engineering, contact engineering, and material integration are given first. Then 2D transistors for certain electronic applications including digital and analog circuits, heterogeneous integration chips, and sensing circuits are discussed. Moreover, several promising applications (artificial intelligence chips and quantum chips) based on specific mechanism devices are introduced. Finally, the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed, and potential development pathways or roadmaps are further speculated and outlooked.

Low-dimensional nanostructures for monolithic 3D-integrated flexible and stretchable electronics

Flexible/stretchable electronics, which are characterized by their ultrathin design, lightweight structure, and excellent mechanical robustness and conformability, have garnered significant attention due to their unprecedented potential in healthcare, advanced robotics, and human-machine interface technologies. An increasing number of low-dimensional nanostructures with exceptional mechanical, electronic, and/or optical properties are being developed for flexible/stretchable electronics to fulfill the functional and application requirements of information sensing, processing, and interactive loops. Compared to the traditional single-layer format, which has a restricted design space, a monolithic three-dimensional (M3D) integrated device architecture offers greater flexibility and stretchability for electronic devices, achieving a high-level of integration to accommodate the state-of-the-art design targets, such as skin-comfort, miniaturization, and multi-functionality. Low-dimensional nanostructures possess small size, unique characteristics, flexible/elastic adaptability, and effective vertical stacking capability, boosting the advancement of M3D-integrated flexible/stretchable systems. In this review, we provide a summary of the typical low-dimensional nanostructures found in semiconductor, interconnect, and substrate materials, and discuss the design rules of flexible/stretchable devices for intelligent sensing and data processing. Furthermore, artificial sensory systems in 3D integration have been reviewed, highlighting the advancements in flexible/stretchable electronics that are deployed with high-density, energy-efficiency, and multi-functionalities. Finally, we discuss the technical challenges and advanced methodologies involved in the design and optimization of low-dimensional nanostructures, to achieve monolithic 3D-integrated flexible/stretchable multi-sensory systems.

Self-Healing, Laminated, and Low Resistance NH3 Sensor Based on 6,6',6″-(Nitrilotris(benzene-4,1-diyl))tris(5-phenylpyrazine-2,3-dicarbonitrile) Sensing Material Operating at Room Temperature

With the rapid development of the concept of the Internet of Things (IoT), gas sensors with the function of simulating the human sense of smell became irreplaceable as a key element. Among them, ammonia (NH3) sensors played an important role in respiration tests, environmental monitoring, safety, and other fields. However, the fabrication of the high-performance device with high stability and resistance to mechanical damages was still a challenge. In this work, polyurethane (PU) with excellent self-healing ability was applied as the substrate, and the sensor was designed from new sensitive material design and device structure optimization, through applying the organic molecule with groups which could absorb NH3 and the laminated structure to shorten the electronic transmission path to achieve a low resistance state and favorable sensing properties. Accordingly, a room temperature flexible NH3 sensor based on 6,6',6″-(nitrilotris(benzene-4,1-diyl))tris(5-phenylpyrazine-2,3-dicarbonitrile) (TPA-3DCNPZ) was successfully developed. The device could self-heal by means of a thermal evaporation assisted method. It exhibited a detection limit of 1 ppm at 98% relative humidity (RH), as well as great stability, selectivity, bending flexibility, and self-healing properties. The improved NH3 sensing performance under high RH was further investigated by complex impedance plots (CIPs) and density functional theory (DFT), attributing to the enhanced adsorption of NH3. The TPA-3DCNPZ based NH3 sensors proved to have great potential for application on simulated exhaled breath to determine the severity of kidney diseases and the progress of treatment. This work also provided new ideas for the construction of high-performance room temperature NH3 sensors.

Pulse irradiation synthesis of metal chalcogenides on flexible substrates for enhanced photothermoelectric performance

High synthesis temperatures and specific growth substrates are typically required to obtain crystalline or oriented inorganic functional thin films, posing a significant challenge for their utilization in large-scale, low-cost (opto-)electronic applications on conventional flexible substrates. Here, we explore a pulse irradiation synthesis (PIS) to prepare thermoelectric metal chalcogenide (e.g., Bi2Se3, SnSe2, and Bi2Te3) films on multiple polymeric substrates. The self-propagating combustion process enables PIS to achieve a synthesis temperature as low as 150 °C, with an ultrafast reaction completed within one second. Beyond the photothermoelectric (PTE) property, the thermal coupling between polymeric substrates and bismuth selenide films is also examined to enhance the PTE performance, resulting in a responsivity of 71.9 V/W and a response time of less than 50 ms at 1550 nm, surpassing most of its counterparts. This PIS platform offers a promising route for realizing flexible PTE or thermoelectric devices in an energy-, time-, and cost-efficient manner.

Self-Rectifying Memristors for Three-Dimensional In-Memory Computing

Costly data movement in terms of time and energy in traditional von Neumann systems is exacerbated by emerging information technologies related to artificial intelligence. In-memory computing (IMC) architecture aims to address this problem. Although the IMC hardware prototype represented by a memristor is developed rapidly and performs well, the sneak path issue is a critical and unavoidable challenge prevalent in large-scale and high-density crossbar arrays, particularly in three-dimensional (3D) integration. As a perfect solution to the sneak-path issue, a self-rectifying memristor (SRM) is proposed for 3D integration because of its superior integration density. To date, SRMs have performed well in terms of power consumption (aJ level) and scalability (>102  Mbit). Moreover, SRM-configured 3D integration is considered an ideal hardware platform for 3D IMC. This review focuses on the progress in SRMs and their applications in 3D memory, IMC, neuromorphic computing, and hardware security. The advantages, disadvantages, and optimization strategies of SRMs in diverse application scenarios are illustrated. Challenges posed by physical mechanisms, fabrication processes, and peripheral circuits, as well as potential solutions at the device and system levels, are also discussed.

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions

Three-dimensional (3D) hetero-integration technology is poised to revolutionize the field of electronics by stacking functional layers vertically, thereby creating novel 3D circuity architectures with high integration density and unparalleled multifunctionality. However, the conventional 3D integration technique involves complex wafer processing and intricate interlayer wiring. Here we demonstrate monolithic 3D integration of two-dimensional, material-based artificial intelligence (AI)-processing hardware with ultimate integrability and multifunctionality. A total of six layers of transistor and memristor arrays were vertically integrated into a 3D nanosystem to perform AI tasks, by peeling and stacking of AI processing layers made from bottom-up synthesized two-dimensional materials. This fully monolithic-3D-integrated AI system substantially reduces processing time, voltage drops, latency and footprint due to its densely packed AI processing layers with dense interlayer connectivity. The successful demonstration of this monolithic-3D-integrated AI system will not only provide a material-level solution for hetero-integration of electronics, but also pave the way for unprecedented multifunctional computing hardware with ultimate parallelism.

Low-Thermal-Budget Ferroelectric Field-Effect Transistors Based on CuInP2S6 and InZnO

In this paper, we demonstrate low-thermal-budget ferroelectric field-effect transistors (FeFETs) based on the two-dimensional ferroelectric CuInP2S6 (CIPS) and oxide semiconductor InZnO (IZO). The CIPS/IZO FeFETs exhibit nonvolatile memory windows of ∼1 V, low off-state drain currents, and high carrier mobilities. The ferroelectric CIPS layer serves a dual purpose by providing electrostatic doping in IZO and acting as a passivation layer for the IZO channel. We also investigate the CIPS/IZO FeFETs as artificial synaptic devices for neural networks. The CIPS/IZO synapse demonstrates a sizable dynamic ratio (125) and maintains stable multilevel states. Neural networks based on CIPS/IZO FeFETs achieve an accuracy rate of over 80% in recognizing MNIST handwritten digits. These ferroelectric transistors can be vertically stacked on silicon complementary metal-oxide semiconductor (CMOS) with a low thermal budget, offering broad applications in CMOS+X technologies and energy-efficient 3D neural networks.

Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors

Carbon nanotube (CNT) transistors demonstrate high mobility but also experience off-state leakage due to the small effective mass and band gap. The lower limit of off-current (IMIN) was measured in electrostatically doped CNT metal-oxide-semiconductor field-effect transistors (MOSFETs) across a range of band gaps (0.37 to 1.19 eV), supply voltages (0.5 to 0.7 V), and extension doping levels (0.2 to 0.8 carriers/nm). A nonequilibrium Green's function (NEGF) model confirms the dependence of IMIN on CNT band gap, supply voltage, and extension doping level. A leakage current design space across CNT band gap, supply voltage, and extension doping is projected based on the validated NEGF model for long-channel CNT MOSFETs to identify the appropriate device design choices. The optimal extension doping and CNT band gap design choice for a target off-current density are identified by including on-current projection in the leakage current design space. An extension doping level >0.5 carrier/nm is required for optimized on-current.

Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

Post-CMOS processing challenges and design developments of CMOS-MEMS microheaters for local CNT synthesis

Carbon nanotubes (CNTs) can be locally grown on custom-designed CMOS microheaters by a thermal chemical vapour deposition (CVD) process to utilize the sensing capabilities of CNTs in emerging micro- and nanotechnology applications. For such a direct CMOS-CNT integration, a key requirement is the development of necessary post-processing steps on CMOS chips for fabricating CMOS-MEMS polysilicon heaters that can locally generate the required CNT synthesis temperatures (~650-900 °C). In our post-CMOS processing, a subtractive fabrication technique is used for micromachining the polysilicon heaters, where the passivation layers in CMOS are used as masks to protect the electronics. For dielectric etching, it is necessary to achieve high selectivity, uniform etching and a good etch rate to fully expose the polysilicon layers without causing damage. We achieved successful post-CMOS processing by developing two-step reactive ion etching (RIE) of the SiO2 dielectric layer and making design improvements to a second-generation CMOS chip. After the dry etching process, CMOS-MEMS microheaters are partially suspended by SiO2 wet etching with minimum damage to the exposed aluminium layers, to obtain high thermal isolation. The fabricated microheaters are then successfully utilized for synthesizing CNTs by a local thermal CVD process. The CMOS post-processing challenges and design aspects to fabricate CMOS-MEMS polysilicon microheaters for such high-temperature applications are detailed in this article. Our developed process for heterogeneous monolithic integration of CMOS-CNT shows promise for wafer-level manufacturing of CNT-based sensors by incorporating additional steps in an already existing foundry CMOS process.

Biotemplated precise assembly approach toward ultra-scaled high-performance electronics

Structural DNA nanotechnology can be programmed into complex designer structures with molecular precision for directing a wide range of inorganic and biological materials. However, the use of DNA-templated approaches for the fabrication and performance requirements of ultra-scaled semiconductor electronics is limited by its assembly disorder and destructive interface composition. In this protocol, using carbon nanotubes (CNTs) as model semiconductors, we provide a stepwise process to build ultra-scaled, high-performance field-effect transistors (FETs) from micron-scale three-dimensional DNA templates. We apply the approach to assemble CNT arrays with uniform pitches scaled between 24.1 and 10.4 nm with yields of more than 95%, which exceeds the resolution limits of conventional lithography. To achieve highly clean CNT interfaces, we detail a rinsing-after-fixing step to remove residual DNA template and salt contaminations present around the contact and the channel regions, without modifying the alignment of the CNT arrays. The DNA-templated CNT FETs display both high on-state current (4-15 μA per CNT) and small subthreshold swing (60-100 mV per decade), which are superior to previous examples of biotemplated electronics and match the performance metrics of high-performance, silicon-based electronics. The scalable assembly of defect-free three-dimensional DNA templates requires 1 week and the CNT arrays can be synthesized within half a day. The interface engineering requires 1-2 d, while the fabrication of high-performance FET and logic gate circuits requires 2-4 d. The structural and performance characterizations of molecular-precise DNA self-assembly and high-performance electronics requires 1-2 d. The protocol is suited for users with expertise in DNA nanotechnology and semiconductor electronics.

Energy Efficient Artificial Olfactory System with Integrated Sensing and Computing Capabilities for Food Spoilage Detection

Artificial olfactory systems (AOSs) that mimic biological olfactory systems are of great interest. However, most existing AOSs suffer from high energy consumption levels and latency issues due to data conversion and transmission. In this work, an energy- and area-efficient AOS based on near-sensor computing is proposed. The AOS efficiently integrates an array of sensing units (merged field effect transistor (FET)-type gas sensors and amplifier circuits) and an AND-type nonvolatile memory (NVM) array. The signals of the sensing units are directly connected to the NVM array and are computed in memory, and the meaningful linear combinations of signals are output as bit line currents. The AOS is designed to detect food spoilage by employing thin zinc oxide films as gas-sensing materials, and it exhibits low detection limits for H2 S and NH3 gases (0.01 ppm), which are high-protein food spoilage markers. As a proof of concept, monitoring the entire spoilage process of chicken tenderloin is demonstrated. The system can continuously track freshness scores and food conditions throughout the spoilage process. The proposed AOS platform is applicable to various applications due to its ability to change the sensing temperature and programmable NVM cells.

CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10's of MHz.

Functionalizing nanophotonic structures with 2D van der Waals materials

The integration of two-dimensional (2D) van der Waals materials with nanostructures has triggered a wide spectrum of optical and optoelectronic applications. Photonic structures of conventional materials typically lack efficient reconfigurability or multifunctionality. Atomically thin 2D materials can thus generate new functionality and reconfigurability for a well-established library of photonic structures such as integrated waveguides, optical fibers, photonic crystals, and metasurfaces, to name a few. Meanwhile, the interaction between light and van der Waals materials can be drastically enhanced as well by leveraging micro-cavities or resonators with high optical confinement. The unique van der Waals surfaces of the 2D materials enable handiness in transfer and mixing with various prefabricated photonic templates with high degrees of freedom, functionalizing as the optical gain, modulation, sensing, or plasmonic media for diverse applications. Here, we review recent advances in synergizing 2D materials to nanophotonic structures for prototyping novel functionality or performance enhancements. Challenges in scalable 2D materials preparations and transfer, as well as emerging opportunities in integrating van der Waals building blocks beyond 2D materials are also discussed.

Four levels of in-sensor computing in bionic olfaction: from discrete components to multi-modal integrations

Sensing and computing are two important ways in which humans attempt to perceive and understand the analog world through digital devices. Analog-to-digital converters (ADCs) discretize analog signals while the data bus transmits digital data between the components of a computer. With the increase in sensor nodes and the application of deep neural networks, the energy and time consumption limit the increment of data throughput. In-sensor computing is a computing paradigm that integrates sensing, storage, and processing in one device without ADCs and data transfer. According to the integration degree, herein, we summarize four levels of in-sensor computing in the field of artificial olfactory. In the first level, we show that different functions are conducted by using discrete components. Next, the data conversion and transfer are exempt within the in-memory computing architecture with necessary data encoding. Subsequently, in-sensor computing is integrated into a single device. Finally, multi-modal in-sensor computing is proposed to improve the quality and reliability of the classification results. At the end of this minireview, we provide an outlook on the use of metal nanoparticle devices to achieve such in-sensor computing for bionic olfaction.

Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T-4R structure for high-density memory

Emerging data-intensive computation has driven the advanced packaging and vertical stacking of integrated circuits, for minimized latency and energy consumption. Yet a monolithic three-dimensional (3D) integrated structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here we experimentally demonstrate a monolithic 3D integration of atomically-thin molybdenum disulfide (MoS2) transistors and 3D vertical resistive random-access memories (VRRAMs), with the MoS2 transistors stacked between the bottom-plane and top-plane VRRAMs. The whole fabrication process is integration-friendly (below 300 °C), and the measurement results confirm that the top-plane fabrication does not affect the bottom-plane devices. The MoS2 transistor can drive each layer of VRRAM into four resistance states. Circuit-level modeling of the monolithic 3D structure demonstrates smaller area, faster data transfer, and lower energy consumption than a planar memory. Such platform holds a high potential for energy-efficient 3D on-chip memory systems.

Tunable non-volatile memories based on 2D InSe/h-BN/GaSe heterostructures towards potential multifunctionality

Floating-gate memories based on two-dimensional van der Waal (2D vdW) heterostructures play an important role in the development of next-generation information technology. The diversity of 2D vdW materials and their heterostructures provides flexibility in the design of novel storage architectures. However, 2D InSe/h-BN/GaSe heterostructures are rarely reported in the field of tunable non-volatile memories, probably due to the quality limitation of materials and complex interfaces from stackings. Herein, a floating-gate 2D InSe/h-BN/GaSe memory with high performance and atmosphere stability is demonstrated. It exhibits both a large ON/OFF current ratio of ∼105 and a good extinction ratio of ∼103, with an estimated maximum storage capacity of 5.1 × 1012 cm-2. Moreover, the storage performance can be regulated by optimizing the thickness of the insulating h-BN layer. Different device configurations have been explored to validate the working mechanism. Furthermore, a simulation of biological synaptic behavior is achieved on the same prototype device. The enhanced non-volatile characteristics enable the exploration of the integrated 2D memory and potential multifunctionality.

Scalable CMOS back-end-of-line-compatible AlScN/two-dimensional channel ferroelectric field-effect transistors

Three-dimensional monolithic integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrent with enhanced energy efficiency in big data applications such as artificial intelligence. Despite decades of efforts, there remains an urgent need for reliable, compact, fast, energy-efficient and scalable memory devices. Ferroelectric field-effect transistors (FE-FETs) are a promising candidate, but requisite scalability and performance in a back-end-of-line process have proven challenging. Here we present back-end-of-line-compatible FE-FETs using two-dimensional MoS2 channels and AlScN ferroelectric materials, all grown via wafer-scalable processes. A large array of FE-FETs with memory windows larger than 7.8 V, ON/OFF ratios greater than 107 and ON-current density greater than 250 μA um-1, all at ~80 nm channel length are demonstrated. The FE-FETs show stable retention up to 10 years by extension, and endurance greater than 104 cycles in addition to 4-bit pulse-programmable memory features, thereby opening a path towards the three-dimensional heterointegration of a two-dimensional semiconductor memory with silicon complementary metal-oxide-semiconductor logic.

In-Sensor Computing: Materials, Devices, and Integration Technologies

The number of sensor nodes in the Internet of Things is growing rapidly, leading to a large volume of data generated at sensory terminals. Frequent data transfer between the sensors and computing units causes severe limitations on the system performance in terms of energy efficiency, speed, and security. To efficiently process a substantial amount of sensory data, a novel computation paradigm that can integrate computing functions into sensor networks should be developed. The in-sensor computing paradigm reduces data transfer and also decreases the high computing complexity by processing data locally. Here, the hardware implementation of the in-sensor computing paradigm at the device and array levels is discussed. The physical mechanisms that lead to unique sensory response characteristics and their corresponding computing functions are illustrated. In particular, bioinspired device characteristics enable the implementation of the functionalities of neuromorphic computation. The integration technology is also discussed and the perspective on the future development of in-sensor computing is provided.

Colloidal robotics

Robots have components that work together to accomplish a task. Colloids are particles, usually less than 100 µm, that are small enough that they do not settle out of solution. Colloidal robots are particles capable of functions such as sensing, computation, communication, locomotion and energy management that are all controlled by the particle itself. Their design and synthesis is an emerging area of interdisciplinary research drawing from materials science, colloid science, self-assembly, robophysics and control theory. Many colloidal robot systems approach synthetic versions of biological cells in autonomy and may find ultimate utility in bringing these specialized functions to previously inaccessible locations. This Perspective examines the emerging literature and highlights certain design principles and strategies towards the realization of colloidal robots.

Optical polarization perturbed by shear strains of ultrasonic bulk waves in anisotropic semiconductors: Multiphysics modeling and optoacoustic validation

Characterization of lattice properties of monocrystalline semiconductors (MS) has been rapidly advanced. Of particular interest is the use of shear strains induced by optoacoustic-bulk-waves. However, this technique has been hindered owing to the lack of quantitative correlations between optoacoustic-bulk-waves-induced shear strains and anisotropic photoelasticity of MS. Motivated by this, a multiphysics model is developed to interrogate the coupling phenomena and interaction between optical polarization and shear strains in MS. With the model, perturbation to the polarization of a monochromatic laser beam, upon interacting with optoacoustic waves in MS, is scrutinized quantitatively. Experimental results are in agreement with those from the model, both revealing the polarization perturbed by shear strains quantitatively depends on the crystal orientation and crystal-structure-related symmetry, which are jointly governed by mechanical/photoelastic/optical anisotropies of MS. The approach has paved a new way for selectively acquiring high-sensitivity shear components of optoacoustic-ultrasonic-waves for in situ, high-definition characterization of anisotropic MS.

3D integration enables ultralow-noise isolator-free lasers in silicon photonics

Photonic integrated circuits are widely used in applications such as telecommunications and data-centre interconnects1-5. However, in optical systems such as microwave synthesizers6, optical gyroscopes7 and atomic clocks8, photonic integrated circuits are still considered inferior solutions despite their advantages in size, weight, power consumption and cost. Such high-precision and highly coherent applications favour ultralow-noise laser sources to be integrated with other photonic components in a compact and robustly aligned format-that is, on a single chip-for photonic integrated circuits to replace bulk optics and fibres. There are two major issues preventing the realization of such envisioned photonic integrated circuits: the high phase noise of semiconductor lasers and the difficulty of integrating optical isolators directly on-chip. Here we challenge this convention by leveraging three-dimensional integration that results in ultralow-noise lasers with isolator-free operation for silicon photonics. Through multiple monolithic and heterogeneous processing sequences, direct on-chip integration of III-V gain medium and ultralow-loss silicon nitride waveguides with optical loss around 0.5 decibels per metre are demonstrated. Consequently, the demonstrated photonic integrated circuit enters a regime that gives rise to ultralow-noise lasers and microwave synthesizers without the need for optical isolators, owing to the ultrahigh-quality-factor cavity. Such photonic integrated circuits also offer superior scalability for complex functionalities and volume production, as well as improved stability and reliability over time. The three-dimensional integration on ultralow-loss photonic integrated circuits thus marks a critical step towards complex systems and networks on silicon.

Aligned Carbon Nanotubes-Based Radiofrequency Transistors for Amplitude Amplification and Frequency Conversion at Millimeter Wave Band

Aligned carbon nanotubes (ACNTs) have been considered as a promising candidate semiconductor with great potential in radiofrequency (RF) electronics due to their high carrier mobility/saturation velocity and small intrinsic capacitance. However, almost all of previously reported works focused on only the cutoff frequency, which is far from enough for practical RF application. In this work, given the speed advantage of ACNTs, we further explore amplitude amplification and frequency conversion capability of ACNTs based RF devices simultaneously, which are two basic functions in RF electronics. Considering there is no de-embedding process for amplification/conversion and reduction power loss, multifinger configuration RF transistors (still having current density around 1 mA/μm) were fabricated with cutoff frequency and maximum oscillation frequency exceeding 150 and 130 GHz, respectively. Based on dedicated ACNTs based RF FETs, we demonstrate almost 7 dB power gain (S₂₁) with over 40 GHz 3-dB bandwidth for amplification and from -12.7 to -17 dB of conversion gain with over 25 dBm IIP3 (input third-order intercept point) of linearity for conversion simultaneously operating at 30 GHz in millimeter wave (mmWave) band both without any tuning instruments and matching technology assistance. The performance achieved here is the best among all the nanomaterials at the mmWave band.

Co-multiplexing spectral and temporal dimensions based on luminescent materials

Optical multiplexing is a pivotal technique for augmenting the capacity of optical data storage (ODS) and increasing the security of anti-counterfeiting. However, due to the dearth of appropriate storage media, optical multiplexing is generally restricted to a single dimension, thus curtailing the encoding capacity. Herein, the co-multiplexing spectral and temporal dimensions are proposed for optical encoding based on photoluminescence (PL) and persistent-luminescence (PersL) at four different wavelengths. Each emission color comprises four luminescence modes. The further multiplexing of four wavelengths leads to the maximum encoding capacity of 8 bits at each pixel. The wavelength difference between adjacent peaks is larger than 50 nm. The well-separated emission wavelengths significantly lower the requirements for high-resolution spectrometers. Moreover, the information is unable to be decoded until both PL and PersL spectra are collected, suggesting a substantial improvement in information security and the security level of anti-counterfeiting.

Thermal Nanoimprint Lithography-A Review of the Process, Mold Fabrication, and Material

Micro- and nanopatterns perform unique functions and have attracted attention in various industrial fields, such as electronic devices, microfluidics, biotechnology, optics, sensors, and smart and anti-adhesion surfaces. To put fine-patterned products to practical use, low-cost patterning technology is necessary. Nanoimprint lithography (NIL) is a promising technique for high-throughput nanopattern fabrication. In particular, thermal nanoimprint lithography (T-NIL) has the advantage of employing flexible materials and eliminating chemicals and solvents. Moreover, T-NIL is particularly suitable for compostable and recyclable materials, especially when applying biobased materials for use in optics and electronics. These attributes make T-NIL an eco-friendly process. However, the processing time of normal T-NIL is longer than that of ultraviolet (UV) NIL using a UV-curable resin because the T-NIL process requires heating and cooling time. Therefore, many studies focus on improving the throughput of T-NIL. Specifically, a T-NIL process based on a roll-to-roll web system shows promise for next-generation nanopatterning techniques because it enables large-area applications with the capability to process webs several meters in width. In this review, the T-NIL process, roll mold fabrication techniques, and various materials are introduced. Moreover, metal pattern transfer techniques using a combination of nanotransfer printing, T-NIL, and a reverse offset are introduced.

The Schottky barrier transistor in emerging electronic devices

This paper explores how the Schottky barrier (SB) transistor is used in a variety of applications and material systems. A discussion of SB formation, current transport processes, and an overview of modeling are first considered. Three discussions follow, which detail the role of SB transistors in high performance, ubiquitous and cryogenic electronics. For high performance computing, the SB typically needs to be minimized to achieve optimal performance and we explore the methods adopted in carbon nanotube technology and two-dimensional electronics. On the contrary for ubiquitous electronics, the SB can be used advantageously in source-gated transistors and reconfigurable field-effect transistors (FETs) for sensors, neuromorphic hardware and security applications. Similarly, judicious use of an SB can be an asset for applications involving Josephson junction FETs.

Monolithic Three-Dimensional Integration of Carbon Nanotube Circuits and Sensors for Smart Sensing Chips

Semiconducting carbon nanotube (CNT) film is a promising material for constructing high-performance complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) and highly sensitive field-effect transistor (FET) bio/chemical sensors. Moreover, CNT logic transistors and sensors can be integrated through a compatible low-temperature fabrication process, providing enough thermal budget to construct monolithic three-dimensional (M3D) systems for smart sensors. However, an M3D sensing chip based on CNT film has not yet been demonstrated. In this work, we develop M3D technology to fabricate CNT CMOS ICs and CNT sensor arrays in two different layers; then, we demonstrate a preliminary M3D sensing system comprising CNT CMOS interfacing ICs in the bottom layer and CNT sensors in the upper layer through interlayer vias as links. As a typical example, a highly sensitive hydrogen sensing IC has been demonstrated to perform in situ sensing and processing functions through upper-layer FET-based hydrogen sensors exposed to the environment and bottom-layer CNT CMOS voltage-controlled oscillator (VCO) interfacing circuits. The M3D CNT sensing ICs convert hydrogen concentration information (8-128 ppm) to digital frequency information (0.78-1.11 GHz) with a sensitivity of 2.75 MHz/ppm. M3D sensing technology is expected to provide a universal sensing system for future smart sensing chips, including multitarget detection and ultralow power sensors.

Reconfigurable Logic-in-Memory Computing Based on a Polarity-Controllable Two-Dimensional Transistor

Logic-in-memory architecture holds great promise to meet the high-performance and energy-efficient requirements of data-intensive scenarios. Two-dimensional compacted transistors embedded with logic functions are expected to extend Moore's law toward advanced nodes. Here we demonstrate that a WSe₂/h-BN/graphene based middle-floating-gate field-effect transistor can perform under diverse current levels due to the controllable polarity by the control gate, floating gate, and drain voltages. Such electrical tunable characteristics are employed for logic-in-memory architectures and can behave as reconfigurable logic functions of AND/XNOR within a single device. Compared to the conventional devices like floating-gate field-effect transistors, our design can greatly decrease the consumption of transistors. For AND/NAND, it can save 75% transistors by reducing the transistor number from 4 to 1; for XNOR/XOR, it is even up to 87.5% with the number being reduced from 8 to 1.

2D materials readiness for the transistor performance breakthrough

As the size of the transistor scales down, this strategy has confronted challenges because of the fundamental limits of silicon materials. Besides, more and more energy and time are consumed by the data transmission out of transistor computing because of the speed mismatching between the computing and memory. To meet the energy efficiency demands of big data computing, the transistor should have a smaller feature size and store data faster to overcome the energy burden of computing and data transfer. Electron transport in two-dimensional (2D) materials is constrained within a 2D plane and different materials are assembled by the van der Waals force. Owning to the atomic thickness and dangling-bond-free surface, 2D materials have demonstrated advantages in transistor scaling-down and heterogeneous structure innovation. In this review, from the performance breakthrough of 2D transistors, we discuss the opportunities, progress and challenges of 2D materials in transistor applications.

Intelligent Multifunctional Sensing Systems based on Ordered Macro-Microporous Metal Organic Framework and Its Derivatives

Compared with nanomaterials-based sensors with single function, the development of multifunctional sensors shows high potential in comprehensive monitoring of personal health and environment, intelligent human-machine interfaces, and realistic imitation of human skin in prosthetics. Ordered macro-microporous metal-organic frameworks (MOFs)-enabled flexible and stretchable electronics are promising candidates for integrated multifunctional sensing systems. Herein, a three-dimensional ordered macro-microporous zeolite imidazolate framework-8 (3DOM ZIF-8) for humidity sensing and the derived ZnO within a hierarchically ordered macroporous-mesoporous-microporous carbon matrix (ZnO@HOMC) for gas sensor is constructed. Benefit from hierarchically ordered macroporous-mesoporous-microporous structure, the active site is fully exposed, and the charge transfer is accelerated. As a result, the multifunctional sensing systems show ultrafast response and recovery speed (10 s and 34 s), high sensitivity (R_air /R_gas = 38.6@50 ppm) to acetone, rapid humidity response speed (0.23 s) within changing humidity (RH 21%-99%), excellent stability and repeatability. Furthermore, in order to realize real-time monitoring of gas concentrations and humidity on mobile devices, an intelligent and portable sensor module is fabricated and wirelessly connected to a smartphone to effectively detect acetone concentration and humidity. This sensing technology shows fascinating applications in personal health, fitness tracking, electronic skins, artificial nervous systems, and human-machine interactions.

Silicon Waveguide-Integrated Carbon Nanotube Photodetector with Low Dark Current and 48 GHz Bandwidth

Low-dimensional materials with excellent optoelectronic properties and complementary metal-oxide-semiconductor (CMOS) process compatibility have the potential to construct high-performance photodetectors used in a cost-efficient monolithic or hybrid integrated optical communication system. Carbon nanotubes (CNTs) have attracted a lot of attention due to special geometric structure and broad band response, high optical absorption coefficient, ps-level intrinsic light response, high carrier mobility and wafer-scaled production process. Here, we demonstrated a high-performance waveguide-integrated CNT photodetector with asymmetric palladium (Pd) and hafnium (Hf) contact electrodes. The ideal photodetector structure was realized via comparing with simulation and experimental results, where the optimized device achieved a high 3 dB bandwidth ∼48 GHz at 0 V, as well as a responsivity ∼73.62 mA/W and dark current ∼0.157 μA at -2 V bias voltage. This waveguide-integrated CNT photodetector with low dark current and high bandwidth is helpful for next-generation optical communication and high-speed optical interconnects.

Three-dimensional inter-layer optical signal transmission realized by a monolithically integrated semiconductor-based carrier transport structure

In this study, we proposed and demonstrated a brand new type of monolithic photonic devices which realizes the three-dimensional (3D) all-optical switching for inter-layer signal transmission. This device is composed of a vertical Si microrod which serves as optical absorption material within a SiN waveguide in one layer and as an index modulation structure within a SiN microdisk resonator lying in the other layer. The ambipolar photo-carrier transport property in the Si microrod was studied by measuring the resonant wavelength shifts under continuous-wave laser pumping. The ambipolar diffusion length can be extracted to be 0.88 µm. Based on the ambipolar photo-carrier transport in a Si microrod through different layers, we presented a fully-integrated all-optical switching operation using this Si microrod and a SiN microdisk with a pump-probe technique through the on-chip SiN waveguides. The switching time windows for the on-resonance operation mode and the off-resonance operation mode can be extracted to be 439 ps and 87 ps, respectively. This device shows potential applications for the future all-optical computing and communication with more practical and flexible configurations in monolithic 3D photonic integrated circuits (3D-PICs).

Chirality-dependent electrical transport properties of carbon nanotubes obtained by experimental measurement

Establishing the relationship between the electrical transport properties of single-wall carbon nanotubes (SWCNTs) and their structures is critical for the design of high-performance SWCNT-based electronic and optoelectronic devices. Here, we systematically investigated the effect of the chiral structures of SWCNTs on their electrical transport properties by measuring the performance of thin-film transistors constructed by eleven distinct (n, m) single-chirality SWCNT films. The results show that, even for SWCNTs with the same diameters but different chiral angles, the difference in the on-state current or carrier mobility could reach an order of magnitude. Further analysis indicates that the electrical transport properties of SWCNTs have strong type and family dependence. With increasing chiral angle for the same-family SWCNTs, Type I SWCNTs exhibit increasing on-state current and mobility, while Type II SWCNTs show the reverse trend. The differences in the electrical properties of the same-family SWCNTs with different chiralities can be attributed to their different electronic band structures, which determine the contact barrier between electrodes and SWCNTs, intrinsic resistance and intertube contact resistance. Our present findings provide an important physical basis for performance optimization and application expansion of SWCNT-based devices.

High-Performance Shortwave Infrared Detector Based on Multilayer Carbon Nanotube Films

Carbon nanotube (CNT) is an ideal candidate material for shortwave infrared (SWIR) detectors due to its large band gap tunability, strong infrared light absorption, and high mobility. Furthermore, the photodetectors based on CNT can be prepared on any substrate using a low-temperature process, which is conducive to three-dimensional (3D) integration. However, owing to the absorption limitation (<2%) of a single-layer network CNT film with low density, the photodetectors of CNT film show low photocurrent responsivity and detectivity. In this paper, we optimize the thickness of the high-purity semiconducting network CNT films to increase the photocurrent responsivity of the photodetectors. When the thickness of network CNT film is about 5 nm, the responsivity of the zero-bias voltage can reach 32 mA/W at 1800 nm wavelength. Then, using stacked CNT films and contact electrode design, the photodetectors exhibit a maximum responsivity of 120 mA/W at 1800 nm wavelength. The photodetectors with stacked CNT films and local n-type channel doping demonstrated a wide response spectral range of 1200-2100 nm, a peak detectivity of 3.94 × 10⁹ Jones at room temperature, and a linear dynamic range over 118 dB. Moreover, the peak detectivity is over 2.27 × 10¹¹ Jones when the temperature is 180 K. Our work demonstrates the potential of the CNT film for future SWIR imaging at a low cost.

Soft Electronics for Health Monitoring Assisted by Machine Learning

Due to the development of the novel materials, the past two decades have witnessed the rapid advances of soft electronics. The soft electronics have huge potential in the physical sign monitoring and health care. One of the important advantages of soft electronics is forming good interface with skin, which can increase the user scale and improve the signal quality. Therefore, it is easy to build the specific dataset, which is important to improve the performance of machine learning algorithm. At the same time, with the assistance of machine learning algorithm, the soft electronics have become more and more intelligent to realize real-time analysis and diagnosis. The soft electronics and machining learning algorithms complement each other very well. It is indubitable that the soft electronics will bring us to a healthier and more intelligent world in the near future. Therefore, in this review, we will give a careful introduction about the new soft material, physiological signal detected by soft devices, and the soft devices assisted by machine learning algorithm. Some soft materials will be discussed such as two-dimensional material, carbon nanotube, nanowire, nanomesh, and hydrogel. Then, soft sensors will be discussed according to the physiological signal types (pulse, respiration, human motion, intraocular pressure, phonation, etc.). After that, the soft electronics assisted by various algorithms will be reviewed, including some classical algorithms and powerful neural network algorithms. Especially, the soft device assisted by neural network will be introduced carefully. Finally, the outlook, challenge, and conclusion of soft system powered by machine learning algorithm will be discussed.

Heterogeneous Integration of Atomically-Thin Indium Tungsten Oxide Transistors for Low-Power 3D Monolithic Complementary Inverter

In this work, the authors demonstrate a novel vertically-stacked thin film transistor (TFT) architecture for heterogeneously complementary inverter applications, composed of p-channel polycrystalline silicon (poly-Si) and n-channel amorphous indium tungsten oxide (a-IWO), with a low footprint than planar structure. The a-IWO TFT with channel thickness of approximately 3-4 atomic layers exhibits high mobility of 24 cm² V^-1 s^-1 , near ideally subthreshold swing of 63 mV dec^-1 , low leakage current below 10^-13 A, high on/off current ratio of larger than 10⁹ , extremely small hysteresis of 0 mV, low contact resistance of 0.44 kΩ-µm, and high stability after encapsulating a passivation layer. The electrical characteristics of n-channel a-IWO TFT are well-matched with p-channel poly-Si TFT for superior complementary metal-oxide-semiconductor technology applications. The inverter can exhibit a high voltage gain of 152 V V^-1 at low supply voltage of 1.5 V. The noise margin can be up to 80% of supply voltage and perform the symmetrical window. The pico-watt static power consumption inverter is achieved by the wide energy bandgap of a-IWO channel and atomically-thin channel. The vertically-stacked complementary field-effect transistors (CFET) with high energy-efficiency can increase the circuit density in a chip to conform the development of next-generation semiconductor technology.

Horizontal Arrays of One-Dimensional van der Waals Heterostructures as Transistor Channels

The nanotube/dielectric interface plays an essential role in achieving superb switching characteristics of carbon nanotube-based transistors for energy-efficient computation. Formation of van der Waals heterostructures with hexagonal boron nitride nanotubes could be an effective means to reduce interface state density, but the need for isolating nanotubes during the formation of coaxial outer layers has hindered the fabrication of their horizontal arrays. Here, we develop a strategy to create isolated heterostructure arrays using aligned carbon nanotubes grown on a quartz substrate as starting materials. Air-suspended arrays of carbon nanotubes are prepared by a dry transfer technique and then used as templates for the coaxial wrapping of boron nitride nanotubes. We then fabricate the transistors, where boron nitride serves as interfacial layers between carbon nanotube channels and conventional gate dielectrics, showing hysteresis-free characteristics owing to the improved interfaces. We have also gained a deeper understanding of the strain applied on inner carbon nanotubes, as well as the inhomogeneity of the outer coating, by characterizing individual heterostructures over trenches and on a substrate surface. The device fabrication and characterization presented here essentially do not require elaborate electron microscopy, thus paving the way for the practical use of one-dimensional van der Waals heterostructures for nanoelectronics.

Structure modulation of two-dimensional transition metal chalcogenides: recent advances in methodology, mechanism and applications

Together with the development of two-dimensional (2D) materials, transition metal dichalcogenides (TMDs) have become one of the most popular series of model materials for fundamental sciences and practical applications. Due to the ever-growing requirements of customization and multi-function, dozens of modulated structures have been introduced in TMDs. In this review, we present a systematic and comprehensive overview of the structure modulation of TMDs, including point, linear and out-of-plane structures, following and updating the conventional classification for silicon and related bulk semiconductors. In particular, we focus on the structural characteristics of modulated TMD structures and analyse the corresponding root causes. We also summarize the recent progress in modulating methods, mechanisms, properties and applications based on modulated TMD structures. Finally, we demonstrate challenges and prospects in the structure modulation of TMDs and forecast potential directions about what and how breakthroughs can be achieved.

Large-scale nano-biosensing technologies

Nanoscale technologies have brought significant advancements to modern diagnostics, enabling unprecedented bio-chemical sensitivities that are key to disease monitoring. At the same time, miniaturized biosensors and their integration across large areas enabled tessellating these into high-density biosensing panels, a key capability for the development of high throughput monitoring: multiple patients as well as multiple analytes per patient. This review provides a critical overview of various nanoscale biosensing technologies and their ability to unlock high testing throughput without compromising detection resilience. We report on the challenges and opportunities each technology presents along this direction and present a detailed analysis on the prospects of both commercially available and emerging biosensing technologies.

Van der Waals Layer Transfer of 2D Materials for Monolithic 3D Electronic System Integration: Review and Outlook

Two-dimensional materials (2DMs) have attracted a great deal of interest due to their immense potential for scientific breakthroughs and technological innovations. While some 2D transition metal dichalcogenides (TMDC) such as MoS₂ and WS₂ are considered as the ultimate channel materials in unltrascaled transistors as replacements for Si, there has also been increasing interest in the monolithic 3D integration of 2DMs on the Si CMOS platform or in flexible electronics as back-end-of-line transistors, memory devices/selectors, and sensors, taking advantage of 2DM properties such as a high current driving capability with low leakage current, nonvolatile switching characteristics, a large surface-to-volume ratio, and a tunable bandgap. However, the realization of both of these scenarios critically depends on the development of manufacturing-viable high-yield 2DM layers transfer from the growth substrate to the Si, since the growth of high-quality 2DM layers often requires a high-temperature growth process on template substrates. Motivated by this, extensive efforts have been made by the 2DM research community to develop various 2DM layer transfer methods, leveraging the van der Waals transfer capability of the layer-structured 2DMs. These efforts have led to a number of successful demonstrations of wafer-scale 2D TMDC layer transfer, while 2DM-enabled template growth/transfer of some functional bulk materials such as III-V, Ge, and AlN has also been demonstrated. This review surveys and compares different 2DM transfer methods developed recently, with a focus on large-area 2D TMDC film transfer along with an introduction of 2DM template-assisted van der Waals growth/transfer of non-2D thin films. We will also briefly present an outlook of our envisioned multifunctionalities in 3D integrated electronic systems enabled by monolithic 3D integration of 2DMs and III-V via van der Waals transfer and discuss possible technology options for overcoming remaining challenges.

In-Depth Physical Mechanism Analysis and Wearable Applications of HfOx-Based Flexible Memristors

Since memristors as an emerging nonlinear electronic component have been considered the most promising candidate for integrating nonvolatile memory and advanced computing technology, the in-depth reveal of the memristive mechanism and the realization of hardware fabrication have facilitated their wide applications in next-generation artificial intelligence. Flexible memristors have shown great promising prospects in wearable electronics and artificial electronic skin (e-skin), but in-depth research on the physical mechanism is still lacking. Here, a flexible memristive device with a Ag/HfO_x/Ti/PET crossbar structure was fabricated, and a remarkable analog switching characteristic similar to synaptic behavior was observed. Through detailed data fitting and in-depth physical mechanism analysis, it is confirmed that the analog switching characteristics of the device are mainly caused by carrier tunneling. Furthermore, the memristive properties of the Ag/HfO_x/Ag/PET device can be attributed to the conductive filaments formed by the redox reaction of the active metal Ag. Finally, the interfacial barrier is extracted by the Arrhenius diagram and the energy band diagram, which is drawn to clearly demonstrate the conduction mechanism of charge trapping in the device. Therefore, the HfO_x-based flexible memristor with analog switching behavior and stable memory performance lays the foundation for cutting-edge applications in wearable electronics and smart e-skin.

Application and Prospect of Artificial Intelligence Methods in Signal Integrity Prediction and Optimization of Microsystems

Microsystems are widely used in 5G, the Internet of Things, smart electronic devices and other fields, and signal integrity (SI) determines their performance. Establishing accurate and fast predictive models and intelligent optimization models for SI in microsystems is extremely essential. Recently, neural networks (NNs) and heuristic optimization algorithms have been widely used to predict the SI performance of microsystems. This paper systematically summarizes the neural network methods applied in the prediction of microsystem SI performance, including artificial neural network (ANN), deep neural network (DNN), recurrent neural network (RNN), convolutional neural network (CNN), etc., as well as intelligent algorithms applied in the optimization of microsystem SI, including genetic algorithm (GA), differential evolution (DE), deep partition tree Bayesian optimization (DPTBO), two stage Bayesian optimization (TSBO), etc., and compares and discusses the characteristics and application fields of the current applied methods. The future development prospects are also predicted. Finally, the article is summarized.