Tunnel field-effect transistors as energy-efficient electronic switches

Identifying atomically thin isolated-band channels for intrinsic steep-slope transistors by high-throughput study

Developing low-power FETs holds significant importance in advancing logic circuits, especially as the feature size of MOSFETs approaches sub-10 nanometers. However, this has been restricted by the thermionic limitation of SS, which is limited to 60 mV per decade at room temperature. Herein, we proposed a strategy that utilizes 2D semiconductors with an isolated-band feature as channels to realize sub-thermionic SS in MOSFETs. Through high-throughput calculations, we established a guiding principle that combines the atomic structure and orbital interaction to identify their sub-thermionic transport potential. This guides us to screen 192 candidates from the 2D material database comprising 1608 systems. Additionally, the physical relationship between the sub-thermionic transport performances and electronic structures is further revealed, which enables us to predict 15 systems with promising device performances for low-power applications with supply voltage below 0.5 V. This work opens a new way for the low-power electronics based on 2D materials and would inspire extensive interests in the experimental exploration of intrinsic steep-slope MOSFETs.

Electric-field tunable Type-I to Type-II band alignment transition in MoSe2/WS2 heterobilayers

Semiconductor heterojunctions are ubiquitous components of modern electronics. Their properties depend crucially on the band alignment at the interface, which may exhibit straddling gap (type-I), staggered gap (type-II) or broken gap (type-III). The distinct characteristics and applications associated with each alignment make it highly desirable to switch between them within a single material. Here we demonstrate an electrically tunable transition between type-I and type-II band alignments in MoSe2/WS2 heterobilayers by investigating their luminescence and photocurrent characteristics. In their intrinsic state, these heterobilayers exhibit a type-I band alignment, resulting in the dominant intralayer exciton luminescence from MoSe2. However, the application of a strong interlayer electric field induces a transition to a type-II band alignment, leading to pronounced interlayer exciton luminescence. Furthermore, the formation of the interlayer exciton state traps free carriers at the interface, leading to the suppression of interlayer photocurrent and highly nonlinear photocurrent-voltage characteristics. This breakthrough in electrical band alignment control, interlayer exciton manipulation, and carrier trapping heralds a new era of versatile optical and (opto)electronic devices composed of van der Waals heterostructures.

A twist for tunable electronic and thermal transport properties of nanodevices

Twisted graphene-layered materials with nonzero interlayer twist angles (θ) have recently become appealing, as they exhibit a range of attractive physical properties, which include a Mott insulating phase and superconductivity. In this study, we consider nanodevices constructed from zigzag graphene nanoribbons with a top rectangular benzenoid [6,3]-flake. Using density functional theory and a non-equilibrium Green's function approach, we explore how the electronic and thermal transport properties in such nanodevices can be tuned through a twist of the top flake by an angle 0° ≤ θ ≤ 8.8° for different stacking configurations. We found a strong dependency of the electronic structure on the stacking type, as well as on the twisting regime, specifically in AA-stacking devices. Electron and hole van Hove singularities (vHSs), which originate, respectively, from the flatness of the top of the valence band for the minor-spin component and the bottom of the conduction band for the major-spin component, are found very close to the Fermi level in the density of states and electronic transmission spectra of AA-stacking devices with a twist angle of 1.1°. We establish that these vHSs in AA-1.1° devices are stable at higher temperatures and, with the increased number of available states, lead to larger values of electron thermal conductivity and finally total thermal conductivity in AA-1.1°. Our work highlights the essential role of twisting and stacking for the fabrication of nanoscale charge and heat switches and spurs future studies of twisted layered structures.

Wide-range and selective detection of SARS-CoV-2 DNA via surface modification of electrolyte-gated IGZO thin-film transistors

The 2019 coronavirus pandemic resulted in a massive global healthcare crisis, highlighting the necessity to develop effective and reproducible platforms capable of rapidly and accurately detecting SARS-CoV-2. In this study, we developed an electrolyte-gated indium-gallium-zinc-oxide (IGZO) thin-film transistor with sequential surface modification to realize the low limit of detection (LoD <50 fM) and a wide detection range from 50 fM to 5 μM with good linearity (R2 = 0.9965), and recyclability. The surface chemical modification was achieved to anchor the single strand of SARS-CoV-2 DNA via selective hybridization. Moreover, the minute electrical signal change following the chemical modification was investigated by in-depth physicochemical analytical techniques. Finally, we demonstrate fully recyclable biosensors based on oxygen plasma treatment. Owing to its cost-effective fabrication, rapid detection at the single-molecule level, and low detection limit, the proposed biosensor can be used as a point-of-care platform to perform timely and effective SARS-CoV-2 detection.

Single-Gate MoS2 Tunnel FET with a Thickness-Modulated Homojunction

Two-dimensional (2D) materials stand as a promising platform for tunnel field-effect transistors (TFETs) in the pursuit of low-power electronics for the Internet of Things era. This promise arises from their dangling bond-free van der Waals heterointerface. Nevertheless, the attainment of high device performance is markedly impeded by the requirement of precise control over the 2D assembly with multiple stacks of different layers. In this study, we addressed a thickness-modulated n/p+-homojunction prepared from Nb-doped p+-MoS2 crystal, where the issue on interface traps can be neglected without any external interface control due to the homojunction. Notably, our observations reveal the existence of a negative differential resistance, even at room temperature (RT). This signifies the successful realization of TFET operation under type III band alignment conditions by a single gate at RT, suggesting that the dominant current mechanism is band-to-band tunneling due to the ideal interface.

Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures

Two-dimensional (2D) semiconductor-based vertical-transport field-effect transistors (VTFETs) - in which the current flows perpendicularly to the substrate surface direction - are in the drive to surmount the stringent downscaling constraints faced by the conventional planar FETs. However, low-power device operation with a sub-60 mV/dec subthreshold swing (SS) at room temperature along with an ultra-scaled channel length remains challenging for 2D semiconductor-based VTFETs. Here, we report steep-slope VTFETs that combine a gate-controllable van der Waals heterojunction and a metal-filamentary threshold switch (TS), featuring a vertical transport channel thinner than 5 nm and sub-thermionic turn-on characteristics. The integrated TS-VTFETs were realised with efficient current switching behaviours, exhibiting a current modulation ratio exceeding 1 × 108 and an average sub-60 mV/dec SS over 6 decades of drain current. The proposed TS-VTFETs with excellent area- and energy-efficiency could help to tackle the performance degradation-device downscaling dilemma faced by logic transistor technologies.

Low-dimensional nanostructures for monolithic 3D-integrated flexible and stretchable electronics

Flexible/stretchable electronics, which are characterized by their ultrathin design, lightweight structure, and excellent mechanical robustness and conformability, have garnered significant attention due to their unprecedented potential in healthcare, advanced robotics, and human-machine interface technologies. An increasing number of low-dimensional nanostructures with exceptional mechanical, electronic, and/or optical properties are being developed for flexible/stretchable electronics to fulfill the functional and application requirements of information sensing, processing, and interactive loops. Compared to the traditional single-layer format, which has a restricted design space, a monolithic three-dimensional (M3D) integrated device architecture offers greater flexibility and stretchability for electronic devices, achieving a high-level of integration to accommodate the state-of-the-art design targets, such as skin-comfort, miniaturization, and multi-functionality. Low-dimensional nanostructures possess small size, unique characteristics, flexible/elastic adaptability, and effective vertical stacking capability, boosting the advancement of M3D-integrated flexible/stretchable systems. In this review, we provide a summary of the typical low-dimensional nanostructures found in semiconductor, interconnect, and substrate materials, and discuss the design rules of flexible/stretchable devices for intelligent sensing and data processing. Furthermore, artificial sensory systems in 3D integration have been reviewed, highlighting the advancements in flexible/stretchable electronics that are deployed with high-density, energy-efficiency, and multi-functionalities. Finally, we discuss the technical challenges and advanced methodologies involved in the design and optimization of low-dimensional nanostructures, to achieve monolithic 3D-integrated flexible/stretchable multi-sensory systems.

Investigation of SiGe/Si heterojunction inductive line tunneling TFET with source Schottky contact for prospect ultra-low power applications

In this paper, a SiGe/Si heterojunction inductive line tunneling tunnel field-effect transistor with source Schottky contact (SC HJLT-iTFET) is proposed and investigated by the Sentaurus Technology Computer Aided Design (TCAD) simulator. By utilizing an appropriate source Schottky metal, the need for multiple ion implantation and annealing steps required for traditional P-I-N TFETs can be avoided, and the problems of self-alignment and random dopant fluctuations (RDF) during ion implantation can be solved. A high ON-state current (ION) is obtained as fully overlapping the source and gate by line tunneling mechanism dominated, the appropriate Si1-xGexmole fraction material in the source region and high-k gate dielectric employed can further improveION. The incorporation of the block layer effectively decreases the lateral electric field at the drain end to reduce the OFF-state current (IOFF). Furthermore, the proposed charge enhancement layer (CEL) on the SiGe channel can suppress the Fermi level pinning effect (FLP) and enhance the charge of the source region. Based on the feasibility of the practical fabrication process, and the rigorous simulations indicate that the device has an SSavgof 19.8 mV/dec and SSminof 6.8 mV/dec atVD= 0.2 V,IONof 2.27 × 10-6Aμm-1, and anION/IOFFratio of 1.02 × 1010, with extremely fast switching speed. These features make the device suitable for future ultra-low power applications on the internet of things, artificial intelligence, and related fields.

Ionic Transistors

Biological voltage-gated ion channels, which behave as life's transistors, regulate ion transport precisely and selectively through atomic-scale selectivity filters to sustain important life activities. By this inspiration, voltage-adaptable ionic transistors that use ions as signal carriers may provide an alternative information processing unit beyond solid-state electronic devices. This review provides a comprehensive overview of the first generation of biomimetic ionic transistors, including their operating mechanisms, device architecture development, and property characterizations. Despite its infancy, significant progress has been made in the applications of ionic transistors in fields such as DNA detection, drug delivery, and ionic circuits. Challenges and prospects of full exploitation of ionic transistors for a broad spectrum of practical applications are also discussed.

Organic iontronic memristors for artificial synapses and bionic neuromorphic computing

To tackle the current crisis of Moore's law, a sophisticated strategy entails the development of multistable memristors, bionic artificial synapses, logic circuits and brain-inspired neuromorphic computing. In comparison with conventional electronic systems, iontronic memristors offer greater potential for the manifestation of artificial intelligence and brain-machine interaction. Organic iontronic memristive materials (OIMs), which possess an organic backbone and exhibit stoichiometric ionic states, have emerged as pivotal contenders for the realization of high-performance bionic iontronic memristors. In this review, a comprehensive analysis of the progress and prospects of OIMs is presented, encompassing their inherent advantages, diverse types, synthesis methodologies, and wide-ranging applications in memristive devices. Predictably, the field of OIMs, as a rapidly developing research subject, presents an exciting opportunity for the development of highly efficient neuro-iontronic systems in areas such as in-sensor computing devices, artificial synapses, and human perception.

Electrostatically Doped Junctionless Graphene Nanoribbon Tunnel Field-Effect Transistor for High-Performance Gas Sensing Applications: Leveraging Doping Gates for Multi-Gas Detection

In this paper, a new junctionless graphene nanoribbon tunnel field-effect transistor (JLGNR TFET) is proposed as a multi-gas nanosensor. The nanosensor has been computationally assessed using a quantum simulation based on the self-consistent solutions of the mode space non-equilibrium Green's function (NEGF) formalism coupled with the Poisson's equation considering ballistic transport conditions. The proposed multi-gas nanosensor is endowed with two top gates ensuring both reservoirs' doping and multi-gas sensing. The investigations have included the IDS-VGS transfer characteristics, the gas-induced electrostatic modulations, subthreshold swing, and sensitivity. The order of change in drain current has been considered as a sensitivity metric. The underlying physics of the proposed JLGNR TFET-based multi-gas nanosensor has also been studied through the analysis of the band diagrams behavior and the energy-position-resolved current spectrum. It has been found that the gas-induced work function modulation of the source (drain) gate affects the n-type (p-type) conduction branch by modulating the band-to-band tunneling (BTBT) while the p-type (n-type) conduction branch still unaffected forming a kind of high selectivity from operating regime point of view. The high sensitivity has been recorded in subthermionic subthreshold swing (SS < 60 mV/dec) regime considering small gas-induced gate work function modulation. In addition, advanced simulations have been performed for the detection of two different types of gases separately and simultaneously, where high-performance has been recorded in terms of sensitivity, selectivity, and electrical behavior. The proposed detection approach, which is viable, innovative, simple, and efficient, can be applied using other types of junctionless tunneling field-effect transistors with emerging channel nanomaterials such as the transition metal dichalcogenides materials. The proposed JLGNRTFET-based multi-gas nanosensor is not limited to two specific gases but can also detect other gases by employing appropriate gate materials in terms of selectivity.

Ultrafast Negative Capacitance Transition for 2D Ferroelectric MoS2 /Graphene Transistor

Negative capacitance gives rise to subthreshold swing (SS) below the fundamental limit by efficient modulation of surface potential in transistors. While negative-capacitance transition is reported in polycrystalline Pb(Zr0.2 Ti0.8 )O3 (PZT) and HfZrO2 (HZO) thin-films in few microseconds timescale, low SS is not persistent over a wide range of drain current when used instead of conventional dielectrics. In this work, the clear nano-second negative transition states in 2D single-crystal CuInP2 S6 (CIPS) flakes have been demonstrated by an alternative fast-transient measurement technique. Further, integrating this ultrafast NC transition with the localized density of states of Dirac contacts and controlled charge transfer in the CIPS/channel (MoS2 /graphene) a state-of-the-art device architecture, negative capacitance Dirac source drain field effect transistor (FET) is introduced. This yields an ultralow SS of 4.8 mV dec-1 with an average sub-10 SS across five decades with on-off ratio exceeding 107 , by simultaneous improvement of transport and body factors in monolayer MoS2 -based FET, outperforming all previous reports. This approach could pave the way to achieve ultralow-SS FETs for future high-speed and low-power electronics.

2D van der Waals Vertical Heterojunction Transistors for Ternary Neural Networks

Compared with binary systems, ternary computing systems can utilize fewer devices to realize the same information density. However, most ternary computing systems based on binary CMOS circuits require additional devices to bridge binary processing and ternary computing. Exploring new device architectures for direct ternary processing and computing becomes the key to promoting ternary computing systems. Here, we demonstrated a 2D van der Waals vertical heterojunction transistor (V-HTR) with three flat conductance states, which can be the basic cell in ternary circuits to perform ternary processing and computing, without additional devices. A ternary neural network (TNN) and a ternary inverter were demonstrated based on the V-HTRs. The TNN can eliminate fuzzy data and output only clear data by building a ternary quantization function. By demonstrating both ternary logic and a TNN on the same device architecture, the 2D V-HTR shows potential as a basic hardware unit for future ternary computing systems.

The device performance limit of in-plane monolayer VTe2/WTe2 heterojunction-based field-effect transistors

To overcome the scaling restriction on silicon-based field-effect transistors (FETs), two-dimensional (2D) transition metal dichalcogenides (TMDs) have been strongly proposed as alternative materials. To explore the device performance limit of TMD-based FETs, in this work, the ab initio quantum transport approach is utilized to study the transport properties of monolayer VTe2/WTe2 heterojunction-based FETs possessing double gates (DGs) with a 5 nm gate length (Lg). Our theoretical simulations demonstrate that the DG-cold-source VTe2/WTe2 FETs with a 5 nm Lg and 2 or 3 nm proper underlap (UL) meet the basic requirements of the on-state current (Ion), power dissipation (PDP), and delay time (τ) for the 2028 needs of the International Technology Roadmap for Semiconductor (ITRS) 2013, which ensures their high-performance and low-power-dissipation device applications. Moreover, the DG-cold-source VTe2/WTe2-based FETs with a 3 nm Lg and 2 or 3 nm UL meet the high-performance requirements of Ion, τ, and PDP for the 2028 needs of ITRS 2013. Additionally, by further considering the negative capacitance technology in devices, the parameters τ, Ion, and PDP of the VTe2/WTe2-based FETs with a 1 nm Lg and 3 nm UL meet well with the 2028 needs for ITRS 2013 towards high-performance device applications. Our theoretical results uncover that the 2D DG-cold-source VTe2/WTe2 FETs can be used as a new kind of promising material candidate to drive the scaling of Moore's law down to 1 nm.

Improved Resistive and Synaptic Characteristics in Neuromorphic Systems Achieved Using the Double-Forming Process

In this study, we investigate the electrical properties of ITO/ZrOx/TaN RRAM devices for neuromorphic computing applications. The thickness and material composition of the device are analyzed using transmission electron microscopy. Additionally, the existence of TaON interface layers was confirmed using dispersive X-ray spectroscopy and X-ray photoelectron analysis. The forming process of the ZrOx-based device can be divided into two categories, namely single- and double forming, based on the initial lattice oxygen vacancies. The resistive switching behaviors of the two forming methods are compared in terms of the uniformity properties of endurance and retention. The rationale behind each I-V forming process was determined as follows: in the double-forming method case, an energy band diagram was constructed using F-N tunneling; conversely, in the single-forming method case, the ratio of oxygen vacancies was extracted based on XPS analysis to identify the conditions for filament formation. Subsequently, synaptic simulations for the applications of neuromorphic systems were conducted using a pulse scheme to achieve potentiation and depression with a deep neural network-based pattern recognition system to display the achieved recognition accuracy. Finally, high-order synaptic plasticity (spike-timing-dependent plasticity (STDP)) is emulated based on the Hebbian rule.

Vertical tunneling FET with Ge/Si doping-less heterojunction, a high-performance switch for digital applications

A vertical tunneling field effect transistor composed of a doping-less tunneling heterojunction and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has an optimized electrostatic control over the channel. We have performed all the numerical simulations using Silvaco ATLAS, calibrated to the verified data of a device with the similar working principle. The impact of the wide range of non-idealities, such as trap-assisted tunneling, interface trap charges, and ambipolar conduction, is thoroughly investigated. We have also evaluated the impact of negative capacitance material to further improve our device switching characteristics. Introducing both n-channel and p-channel devices, and employing them into a 6T SRAM circuit, we have investigated its performance in terms of parameters like read and write SNM. The FOMs such as Ion = 34.4 µA/µm, Ion/Ioff = 7.17 × 107, and fT = 123 GHz show that our proposed device is a notable candidate for both DC and RF applications.

Enhancing subthreshold slope and ON-current in a simple iTFET with overlapping gate on source-contact, drain Schottky contact, and intrinsic SiGe-pocket

In this paper, we present a new novel simple iTFET with overlapping gate on source-contact (SGO), Drain Schottky Contact, and intrinsic SiGe pocket (Pocket-SGO iTFET). The aim is to achieve steep subthreshold swing (S.S) and high ION current. By optimizing the gate and source-contact overlap, the tunneling efficiency is significantly enhanced, while the ambipolar effect is suppressed. Additionally, using a Schottky contact at the drain/source, instead of ion implantation drain/source, reduces leakage current and thermal budget. Moreover, the tunneling region is replaced by an intrinsic SiGe pocket posing a narrower bandgap, which increases the probability of band-to-band tunneling and enhances the ION current. Our simulations are based on the feasibility of the actual process, thorough Sentaurus TCAD simulations demonstrate that the Pocket-SGO iTFET exhibits an average and minimum subthreshold swing of S.Savg = 16.2 mV/Dec and S.Smin = 4.62 mV/Dec, respectively. At VD = 0.2 V, the ION current is 1.81 [Formula: see text] 10-6 A/μm, and the ION/IOFF ratio is 1.34 [Formula: see text] 109. The Pocket-SGO iTFET design shows great potential for ultra-low-power devices that are required for the Internet of Things (IoT) and AI applications.

Harnessing the Metal-Insulator Transition of VO2 in Neuromorphic Computing

Future-generation neuromorphic computing seeks to overcome the limitations of von Neumann architectures by colocating logic and memory functions, thereby emulating the function of neurons and synapses in the human brain. Despite remarkable demonstrations of high-fidelity neuronal emulation, the predictive design of neuromorphic circuits starting from knowledge of material transformations remains challenging. VO2 is an attractive candidate since it manifests a near-room-temperature, discontinuous, and hysteretic metal-insulator transition. The transition provides a nonlinear dynamical response to input signals, as needed to construct neuronal circuit elements. Strategies for tuning the transformation characteristics of VO2 based on modification of material properties, interfacial structure, and field couplings, are discussed. Dynamical modulation of transformation characteristics through in situ processing is discussed as a means of imbuing synaptic function. Mechanistic understanding of site-selective modification; external, epitaxial, and chemical strain; defect dynamics; and interfacial field coupling in modifying local atomistic structure, the implications therein for electronic structure, and ultimately, the tuning of transformation characteristics, is emphasized. Opportunities are highlighted for inverse design and for using design principles related to thermodynamics and kinetics of electronic transitions learned from VO2 to inform the design of new Mott materials, as well as to go beyond energy-efficient computation to manifest intelligence.

Reversible Diode with Tunable Band Alignment for Photoelectricity-Induced Artificial Synapse

The advent of big data era has put forward higher requirements for electronic nanodevices that have low energy consumption for their application in analog computing with memory and logic circuit to address attendant energy efficiency issues. Here, a miniaturized diode with a reversible switching state based on N-n MoS2 homojunction used a bandgap renormalization effect through the band alignment type regulated by both dielectric and polarization, controllably switched between type-I and type-II, which can be simulated as artificial synapse for sensing memory processing because of its rectification, nonvolatile characteristic and high optical responsiveness. The device demonstrates a rectification ratio of 103 . When served as memory retention time, it can attain at least 7000 s. For the synapse simulation, it has an ultralow-level energy consumption because of the pA-level operation current with 5 pJ for long-term potentiation and 7.8 fJ for long-term depression. Furthermore, the paired pulse facilitation index reaches up to 230%, and it realizes the function of optical storage that can be applied to simulate visual cells.

A new line tunneling SiGe/Si iTFET with control gate for leakage suppression and subthreshold swing improvement

This article presents a new line tunneling dominating metal-semiconductor contact-induced SiGe-Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given a sufficient negative bias, the overlap of the energy bands at the drain in the OFF-state is effectively suppressed, thus reducing the tunneling probability and significantly decreasing leakage current. Additionally, the large overlap area between the source and gate improves the gate's ability to control the tunneling interface effectively, improving the ON-state current and subthreshold swing characteristics. By using the Schottky contact characteristics of a metal-semiconductor contact with different work functions to form a PN junction, the need to control doping profiles or random doping fluctuations is avoided. Furthermore, as ion implantation is not required, issues related to subsequent annealing are also eliminated, greatly reducing thermal budget. Due to the different material bandgap characteristics selected for the source and drain regions, the probability of overlap of the energy bands in the source region in the ON-state is increased and that in the drain region in the OFF-state is reduced. Based on the feasibility of the actual fabrication process and through rigorous 2D simulation studies, improvements in subthreshold swing and high on/off current ratio can be achieved simultaneously based on the proposed device structure. Additionally, the presence of the control gate structure effectively suppresses leakage current, further enhancing its potential for low-power-consumption applications.

Piezotronic and Piezo-Phototronic Effects-Enhanced Core-Shell Structure-Based Nanowire Field-Effect Transistors

Piezotronic and piezo-phototronic effects have been extensively applied to modulate the performance of advanced electronics and optoelectronics. In this study, to systematically investigate the piezotronic and piezo-phototronic effects in field-effect transistors (FETs), a core-shell structure-based Si/ZnO nanowire heterojunction FET (HJFET) model was established using the finite element method. We performed a sweep analysis of several parameters of the model. The results show that the channel current increases with the channel radial thickness and channel doping concentration, while it decreases with the channel length, gate doping concentration, and gate voltage. Under a tensile strain of 0.39‱, the saturation current change rate can reach 38%. Finally, another core-shell structure-based ZnO/Si nanowire HJFET model with the same parameters was established. The simulation results show that at a compressive strain of -0.39‱, the saturation current change rate is about 18%, which is smaller than that of the Si/ZnO case. Piezoelectric potential and photogenerated electromotive force jointly regulate the carrier distribution in the channel, change the width of the channel depletion layer and the channel conductivity, and thus regulate the channel current. The research results provide a certain degree of reference for the subsequent experimental design of Zn-based HJFETs and are applicable to other kinds of FETs.

Improved Electrical Characteristics of Field Effect Transistors with GeSeTe-Based Ovonic Threshold Switching Devices

Hyper-field effect transistors (hyper-FETs) are crucial in the development of low-power logic devices. With the increasing significance of power consumption and energy efficiency, conventional logic devices can no longer achieve the required performance and low-power operation. Next-generation logic devices are designed based on complementary metal-oxide-semiconductor circuits, and the subthreshold swing of existing metal-oxide semiconductor field effect transistors (MOSFETs) cannot be reduced below 60 mV/dec at room temperature owing to the thermionic carrier injection mechanism in the source region. Therefore, new devices must be developed to overcome these limitations. In this study, we present a novel threshold switch (TS) material, which can be applied to logic devices by employing ovonic threshold switch (OTS) materials, failure control of insulator-metal transition materials, and structural optimization. The proposed TS material is connected to a FET device to evaluate its performance. The results demonstrate that commercial transistors connected in series with GeSeTe-based OTS devices exhibit significantly lower subthreshold swing values, high on/off current ratios, and high durability of up to 10⁸.

Dielectrics for Two-Dimensional Transition-Metal Dichalcogenide Applications

Despite over a decade of intense research efforts, the full potential of two-dimensional transition-metal dichalcogenides continues to be limited by major challenges. The lack of compatible and scalable dielectric materials and integration techniques restrict device performances and their commercial applications. Conventional dielectric integration techniques for bulk semiconductors are difficult to adapt for atomically thin two-dimensional materials. This review provides a brief introduction into various common and emerging dielectric synthesis and integration techniques and discusses their applicability for 2D transition metal dichalcogenides. Dielectric integration for various applications is reviewed in subsequent sections including nanoelectronics, optoelectronics, flexible electronics, valleytronics, biosensing, quantum information processing, and quantum sensing. For each application, we introduce basic device working principles, discuss the specific dielectric requirements, review current progress, present key challenges, and offer insights into future prospects and opportunities.

2D materials readiness for the transistor performance breakthrough

As the size of the transistor scales down, this strategy has confronted challenges because of the fundamental limits of silicon materials. Besides, more and more energy and time are consumed by the data transmission out of transistor computing because of the speed mismatching between the computing and memory. To meet the energy efficiency demands of big data computing, the transistor should have a smaller feature size and store data faster to overcome the energy burden of computing and data transfer. Electron transport in two-dimensional (2D) materials is constrained within a 2D plane and different materials are assembled by the van der Waals force. Owning to the atomic thickness and dangling-bond-free surface, 2D materials have demonstrated advantages in transistor scaling-down and heterogeneous structure innovation. In this review, from the performance breakthrough of 2D transistors, we discuss the opportunities, progress and challenges of 2D materials in transistor applications.

Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits.

Graphene Strain-Effect Transistor with Colossal ON/OFF Current Ratio Enabled by Reversible Nanocrack Formation in Metal Electrodes on Piezoelectric Substrates

Extraordinarily high carrier mobility in graphene has led to many remarkable discoveries in physics and at the same time invoked great interest in graphene-based electronic devices and sensors. However, the poor ON/OFF current ratio observed in graphene field-effect transistors has stymied its use in many applications. Here, we introduce a graphene strain-effect transistor (GSET) with a colossal ON/OFF current ratio in excess of 10⁷ by exploiting strain-induced reversible nanocrack formation in the source/drain metal contacts with the help of a piezoelectric gate stack. GSETs also exhibit steep switching with a subthreshold swing (SS) < 1 mV/decade averaged over ∼6 orders of magnitude change in the source-to-drain current for both electron and hole branch amidst a finite hysteresis window. We also demonstrate high device yield and strain endurance for GSETs. We believe that GSETs can significantly expand the application space for graphene-based technologies beyond what is currently envisioned.

Laser-Induced Phase Transition and Patterning of hBN-Encapsulated MoTe2

Transition metal dichalcogenides exhibit phase transitions through atomic migration when triggered by various stimuli, such as strain, doping, and annealing. However, since atomically thin 2D materials are easily damaged and evaporated from these strategies, studies on the crystal structure and composition of transformed 2D phases are limited. Here, the phase and composition change behavior of laser-irradiated molybdenum ditelluride (MoTe₂ ) in various stacked geometry are investigated, and the stable laser-induced phase patterning in hexagonal boron nitride (hBN)-encapsulated MoTe₂ is demonstrated. When air-exposed or single-side passivated 2H-MoTe₂ are irradiated by a laser, MoTe₂ is transformed into Te or Mo₃ Te₄ due to the highly accumulated heat and atomic evaporation. Conversely, hBN-encapsulated 2H-MoTe₂ transformed into a 1T' phase without evaporation or structural degradation, enabling stable phase transitions in desired regions. The laser-induced phase transition shows layer number dependence; thinner MoTe₂ has a higher phase transition temperature. From the stable phase patterning method, the low contact resistivity of 1.13 kΩ µm in 2H-MoTe₂ field-effect transistors with 1T' contacts from the seamless heterophase junction geometry is achieved. This study paves an effective way to fabricate monolithic 2D electronic devices with laterally stitched phases and provides insights into phase and compositional changes in 2D materials.

Carbon nanomaterial-involved EMT and CSC in cancer

Carbon nanomaterials (CNMs) are ubiquitous in our daily lives because of the outstanding physicochemical properties. CNMs play curial parts in industrial and medical fields, however, the risks of CNMs exposure to human health are still not fully understood. In view of, it is becoming extremely difficult to ignore the existence of the toxicity of CNMs. With the increasing exploitation of CNMs, it's necessary to evaluate the potential impact of these materials on human health. In recent years, more and more researches have shown that CNMs are contributed to the cancer formation and metastasis after long-term exposure through epithelial-mesenchymal transition (EMT) and cancer stem cells (CSCs) which is associated with cancer progression and invasion. This review discusses CNMs properties and applications in industrial and medical fields, adverse effects on human health, especially the induction of tumor initiation and metastasis through EMT and CSCs procedure.

Three-dimensional inter-layer optical signal transmission realized by a monolithically integrated semiconductor-based carrier transport structure

In this study, we proposed and demonstrated a brand new type of monolithic photonic devices which realizes the three-dimensional (3D) all-optical switching for inter-layer signal transmission. This device is composed of a vertical Si microrod which serves as optical absorption material within a SiN waveguide in one layer and as an index modulation structure within a SiN microdisk resonator lying in the other layer. The ambipolar photo-carrier transport property in the Si microrod was studied by measuring the resonant wavelength shifts under continuous-wave laser pumping. The ambipolar diffusion length can be extracted to be 0.88 µm. Based on the ambipolar photo-carrier transport in a Si microrod through different layers, we presented a fully-integrated all-optical switching operation using this Si microrod and a SiN microdisk with a pump-probe technique through the on-chip SiN waveguides. The switching time windows for the on-resonance operation mode and the off-resonance operation mode can be extracted to be 439 ps and 87 ps, respectively. This device shows potential applications for the future all-optical computing and communication with more practical and flexible configurations in monolithic 3D photonic integrated circuits (3D-PICs).

A steep-switching impact ionization-based threshold switching field-effect transistor

A steep switching device with a low subthreshold swing (SS) that overcomes the fundamental Boltzmann limit (kT/q) is required to efficiently process a continuously increasing amount of data. Recently, two-dimensional material-based impact ionization transistors with various structures have been reported with the advantages of a low critical electric field and a unique quantum confinement effect. However, most of them cannot retain steep switching at room temperature, and device performance degradation issues caused by impact ionization-induced hot carriers have not been structurally addressed. In this study, we presented an impact-ionization-based threshold switching field-effect transistor (I²S-FET) fabricated with a serial connection of a MoS₂ FET and WSe₂ impact ionization-based threshold switch (I²S). We obtained repetitive operation with low SS (32.8 mV dec^-1) at room temperature, along with low dielectric injection efficiency (10^-6), through a structural design with separation of the conducting region, which determines on-state carrier transport, and the steep-switching region where the transition from off- to on-state occurs via impact ionization. Furthermore, compared to previously reported threshold-switching devices, our device demonstrated hysteresis-free switching characteristics. This study provides a promising approach for developing next-generation energy-efficient electronic devices and ultralow-power applications.

Anisotropy of impact ionization in WSe2 field effect transistors

Carrier multiplication via impact ionization in two-dimensional (2D) layered materials is a very promising process for manufacturing high-performance devices because the multiplication has been reported to overcome thermodynamic conversion limits. Given that 2D layered materials exhibit highly anisotropic transport properties, understanding the directionally-dependent multiplication process is necessary for device applications. In this study, the anisotropy of carrier multiplication in the 2D layered material, WSe₂, is investigated. To study the multiplication anisotropy of WSe₂, both lateral and vertical WSe₂ field effect transistors (FETs) are fabricated and their electrical and transport properties are investigated. We find that the multiplication anisotropy is much bigger than the transport anisotropy, i.e., the critical electric field (E_CR) for impact ionization of vertical WSe₂ FETs is approximately ten times higher than that of lateral FETs. To understand the experimental results we calculate the average energy of the carriers in the proposed devices under strong electric fields by using the Monte Carlo simulation method. The calculated average energy is strongly dependent on the transport directions and we find that the critical electric field for impact ionization in vertical devices is approximately one order of magnitude larger than that of the lateral devices, consistent with experimental results. Our findings provide new strategies for the future development of low-power electric and photoelectric devices.

Sensing single domains and individual defects in scaled ferroelectrics

Ultra-scaled ferroelectrics are desirable for high-density nonvolatile memories and neuromorphic computing; however, for advanced applications, single domain dynamics and defect behavior need to be understood at scaled geometries. Here, we demonstrate the integration of a ferroelectric gate stack on a heterostructure tunnel field-effect transistor (TFET) with subthermionic operation. On the basis of the ultrashort effective channel created by the band-to-band tunneling process, the localized potential variations induced by single domains and individual defects are sensed without physical gate-length scaling required for conventional transistors. We electrically measure abrupt threshold voltage shifts and quantify the appearance of new individual defects activated by the ferroelectric switching. Our results show that ferroelectric films can be integrated on heterostructure devices and indicate that the intrinsic electrostatic control within ferroelectric TFETs provides the opportunity for ultrasensitive scale-free detection of single domains and defects in ultra-scaled ferroelectrics. Our approach opens a previously unidentified path for investigating the ultimate scaling limits of ferroelectronics.

Electric Field and Strain Tuning of 2D Semiconductor van der Waals Heterostructures for Tunnel Field-Effect Transistors

Heterostacks consisting of low-dimensional materials are attractive candidates for future electronic nanodevices in the post-silicon era. In this paper, using first-principles calculations based on density functional theory (DFT), we explore the structural and electronic properties of MoTe₂/ZrS₂ heterostructures with various stacking patterns and thicknesses. Our simulations show that the valence band (VB) edge of MoTe₂ is almost aligned with the conduction band (CB) edge of ZrS₂, and (MoTe₂)_m/(ZrS₂)_m (m = 1, 2) heterostructures exhibit the long-sought broken gap band alignment, which is pivotal for realizing tunneling transistors. Electrons are found to spontaneously flow from MoTe₂ to ZrS₂, and the system resembles an ultrascaled parallel plate capacitor with an intrinsic electric field pointed from MoTe₂ to ZrS₂. The effects of strain and external electric fields on the electronic properties are also investigated. For vertical compressive strains, the charge transfer increases due to the decreased coupling between the layers, whereas tensile strains lead to the opposite behavior. For negative electric fields a transition from the type-III to the type-II band alignment is induced. In contrast, by increasing the positive electric fields, a larger overlap between the valence and conduction bands is observed, leading to a larger band-to-band tunneling (BTBT) current. Low-strained heterostructures with various rotation angles between the constituent layers are also considered. We find only small variations in the energies of the VB and CB edges with respect to the Fermi level, for different rotation angles up to 30°. Overall, our simulations offer insights into the fundamental properties of low-dimensional heterostructures and pave the way for their future application in energy-efficient electronic nanodevices.

Hexagonal Boron Nitride for Next-Generation Photonics and Electronics

Hexagonal boron nitride (h-BN), an insulating 2D layered material, has recently attracted tremendous interest motivated by the extraordinary properties it shows across the fields of optoelectronics, quantum optics, and electronics, being exotic material platforms for various applications. At an early stage of h-BN research, it is explored as an ideal substrate and insulating layers for other 2D materials due to its atomically flat surface that is free of dangling bonds and charged impurities, and its high thermal conductivity. Recent discoveries of structural and optical properties of h-BN have expanded potential applications into emerging electronics and photonics fields. h-BN shows a very efficient deep-ultraviolet band-edge emission despite its indirect-bandgap nature, as well as stable room-temperature single-photon emission over a wide wavelength range, showing a great potential for next-generation photonics. In addition, h-BN is extensively being adopted as active media for low-energy electronics, including nonvolatile resistive switching memory, radio-frequency devices, and low-dielectric-constant materials for next-generation electronics.

An Ultra-steep Slope Two-dimensional Strain Effect Transistor

We introduce a high-performance and ultra-steep slope switch, referred to as strain effect transistor (SET), with a subthreshold swing < 0.68 mV/decade at room temperature for 7 orders of magnitude change in the source-to-drain current based on atomically thin 1T'-MoTe₂ as the channel material, piezoelectric lead zirconate titanate (PZT) as the gate dielectric, and nickel (Ni) as the source/drain contact metal. We exploit gate-voltage induced strain transduction in PZT leading to abrupt and reversible cracking of the metal contacts to achieve the abrupt switching. The SET also exhibits a low OFF-state current < 1 pA/μm, a high ON-state current > 1.8 mA/μm at a supply voltage of 1 V, a large current ON/OFF ratio > 1 × 10⁹, and a high transconductance of > 100 μS/μm. The switching delay for the SET was found to be < 5 μs, and no device failure was observed even after 1 million (1 × 10⁶) switching cycles.

Steep-Slope and Hysteresis-Free MoS2 Negative-Capacitance Transistors Using Single HfZrAlO Layer as Gate Dielectric

An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is not conductive to the scaling down of devices. In this study, a steep-slope and hysteresis-free MoS₂ NCFET is fabricated using a single Hf_0.5-xZr_0.5-xAl_2xO_y (HZAO) layer as the gate dielectric. By incorporating several Al atoms into the Hf_0.5Zr_0.5O₂ (HZO) thin film, negative capacitance and positive capacitance can be achieved simultaneously in the HZAO thin film and good capacitance matching can be achieved. This results in excellent electrical performance of the relevant NCFETs, including a low sub-threshold swing of 22.3 mV/dec over almost four orders of drain-current magnitude, almost hysteresis-free, and a high on/off current ratio of 9.4 × 10⁶. Therefore, using a single HZAO layer as the gate dielectric has significant potential in the fabrication of high-performance and low-power dissipation NCFETs compared to conventional HZO/Al₂O₃ stack gates.

The Trend of 2D Transistors toward Integrated Circuits: Scaling Down and New Mechanisms

2D transition metal chalcogenide (TMDC) materials, such as MoS₂ , have recently attracted considerable research interest in the context of their use in ultrascaled devices owing to their excellent electronic properties. Microprocessors and neural network circuits based on MoS₂ have been developed at a large scale but still do not have an advantage over silicon in terms of their integrated density. In this study, the current structures, contact engineering, and doping methods for 2D TMDC materials for the scaling-down process and performance optimization are reviewed. Devices are introduced according to a new mechanism to provide the comprehensive prospects for the use of MoS₂ beyond the traditional complementary-metal-oxide semiconductor in order to summarize obstacles to the goal of developing high-density and low-power integrated circuits (ICs). Finally, prospects for the use of MoS₂ in large-scale ICs from the perspectives of the material, system performance, and application to nonlogic functionalities such as sensor circuits and analogous circuits, are briefly analyzed. The latter issue is along the direction of "more than Moore" research.

Ferroelectric Nanogap-Based Steep-Slope Ambipolar Transistor

The subthreshold swing (SS) of metal-oxide-semiconductor field-effect transistors is limited to 60 mV dec^-1 at room temperature by the Boltzmann tyranny, which restricts the scaling of the supply voltage. A nanogap-based transistor employs a switchable nanoscale air gap as the channel, offering a steep-slope switching process. Meanwhile, nanogaps featuring even sub-3 nm can efficiently block the current flow, exhibiting the potential for tackling the short-channel effect. Here, an electrically switchable ferroelectric nanogap to construct steep-slope transistors, is exploited. An average SS of 15.9 mV dec^-1 across 5 orders and a minimum SS of 13.23 mV dec^-1 are obtained in the high current density range. The transistor exhibits excellent performance with near-zero off-state leakage current and a maximum on-state current of 202 µA µm^-1 at V_DS  = 0.5 V. In addition, the transistor can turn off with either a positive or negative increase in the gate voltage, exhibiting ambipolar characteristics.

Chemical Vapor Deposition of Quaternary 2D BiCuSeO p-Type Semiconductor with Intrinsic Degeneracy

2D BiCuSeO is an intrinsic p-type degenerate semiconductor due to its self-doping effect, which possesses great potential to fabricate high-performance 2D-2D tunnel field-effect transistors (TFETs). However, the controllable synthesis of multinary 2D materials by chemical vapor deposition (CVD) is still a challenge due to the restriction of thermodynamics. Here, the CVD synthesis of quaternary 2D BiCuSeO nanosheets is realized. As-grown BiCuSeO nanosheets with thickness down to ≈6.1 nm (≈7 layers) and domain size of ≈277 µm show excellent ambient stability. Intrinsic p-type degeneracy of BiCuSeO, capable of maintaining even in a few layers, is comprehensively unveiled. By varying the thicknesses and temperatures, the carrier concentration of BiCuSeO nanosheets can be adjusted in the range of 10¹⁹ to 10²¹ cm^-3 , and the Hall mobility of BiCuSeO is ≈191 cm² V^-1 s^-1 (at 2 K). Furthermore, taking advantage of the p-type degeneracy of BiCuSeO, a prototypical BiCuSeO/MoS₂ TFET is fabricated. The emergence of the negative differential resistance trend and multifunctional diodes by modulating the gate voltage and temperature reveal the great practical implementation potential of BiCuSeO nanosheets. These results pave way for the CVD synthesis of multinary 2D materials and rational design of high-performance tunnel devices.

Automated Computer Vision-Enabled Manufacturing of Nanowire Devices

We present a high-throughput method for identifying and characterizing individual nanowires and for automatically designing electrode patterns with high alignment accuracy. Central to our method is an optimized machine-readable, lithographically processable, and multi-scale fiducial marker system─dubbed LithoTag─which provides nanostructure position determination at the nanometer scale. A grid of uniquely defined LithoTag markers patterned across a substrate enables image alignment and mapping in 100% of a set of >9000 scanning electron microscopy (SEM) images (>7 gigapixels). Combining this automated SEM imaging with a computer vision algorithm yields location and property data for individual nanowires. Starting with a random arrangement of individual InAs nanowires with diameters of 30 ± 5 nm on a single chip, we automatically design and fabricate >200 single-nanowire devices. For >75% of devices, the positioning accuracy of the fabricated electrodes is within 2 pixels of the original microscopy image resolution. The presented LithoTag method enables automation of nanodevice processing and is agnostic to microscopy modality and nanostructure type. Such high-throughput experimental methodology coupled with data-extensive science can help overcome the characterization bottleneck and improve the yield of nanodevice fabrication, driving the development and applications of nanostructured materials.

Van der Waals-Interface-Dominated All-2D Electronics

The interface is the device. As the feature size rapidly shrinks, silicon-based electronic devices are facing multiple challenges of material performance decrease and interface quality degradation. Ultrathin 2D materials are considered as potential candidates in future electronics by their atomically flat surfaces and excellent immunity to short-channel effects. Moreover, due to naturally terminated surfaces and weak van der Waals (vdW) interactions between layers, 2D materials can be freely stacked without the lattice matching limit to form high-quality heterostructure interfaces with arbitrary components and twist angles. Controlled interlayer band alignment and optimized interfacial carrier behavior allow all-2D electronics based on 2D vdW interfaces to exhibit more comprehensive functionality and better performance. Especially, achieving the same computing capacity of multiple conventional devices with small footprint all-2D devices is considered to be the key development direction of future electronics. Herein, the unique properties of all-2D vdW interfaces and their construction methods are systematically reviewed and the main performance contributions of different vdW interfaces in 2D electronics are summarized, respectively. Finally, the recent progress and challenges for all-2D vdW electronics are discussed, and how to improve the compatibility of 2D material devices with silicon-based industrial technology is pointed out as a critical challenge.

Microelectronic current-sourcing device based on band-to-band tunneling current

A new stable current-sourcing transistor is developed using the band-to-band tunneling phenomenon. A heterojunction between thin film WS₂and heavily hole-doped bulk silicon converts a section of the WS₂contacting the silicon into a hole-doped WS₂inside the WS₂channel, and band-to-band tunneling occurs between the electron-doped and hole-doped WS₂. The output current is regulated by the tunneling barrier thickness. The thickness depends on the gate bias for device switching, but is less sensitive to the source bias, enabling stable output currents. The minimum line sensitivity is 2.6%, and the temperature coefficient is 1.4 × 10³ppm°C^-1. The device can be operated as a current sourcing device with an ultralow output current and power consumption.

Ambipolar steep-slope nanotransistors with Janus MoSSe/graphene heterostructures

The transfer characteristics and switching mechanism of the steep-slope transistor composed of the graphene/Janus MoSSe heterostructure are investigated by quantum transport calculation. The Schottky barrier height at the Gr/SMoSe interface and tunneling width between the channel and drain can be tuned by the gate voltage, so that the device exhibits ambipolar switching with two minima in the subthreshold swing slope. 34 and 29 mV decade^-1subthreshold swings can be achieved and the on/off ratios are over 10⁶and 10⁸for the different switching mechanisms. The device provides a solution and guidance for the future design of low-power, high-performance devices.

A Novel L-Gate InGaAs/GaAsSb TFET with Improved Performance and Suppressed Ambipolar Effect

A heterojunction tunneling field effect transistor with an L-shaped gate (HJ-LTFET), which is very applicable to operate at low voltage, is proposed and studied by TCAD tools in this paper. InGaAs/GaAsSb heterojunction is applied in HJ-LTFET to enhance the ON-state current (I_ON). Owing to the quasi-broken gap energy band alignment of InGaAs/GaAsSb heterojunction, height and thickness of tunneling barrier are greatly reduced. However, the OFF-state leakage current (I_OFF) also increases significantly due to the reduced barrier height and thickness and results in an obvious source-to-drain tunneling (SDT). In order to solve this problem, an HfO2 barrier layer is inserted between source and drain. Result shows that the insertion layer can greatly suppress the horizontal tunneling leakage appears at the source and drain interface. Other optimization studies such as work function modulation, doping concentration optimization, scaling capability, and analog/RF performance analysis are carried out, too. Finally, the HJ-LTFET with a large I_ON of 213 μA/μm, a steep average SS of 8.9 mV/dec, and a suppressed I_OFF of 10^-12 μA/μm can be obtained. Not only that, but the fT and GBP reached the maximum values of 68.3 GHz and 7.3 GHz under the condition of Vd = 0.5 V, respectively.

Investigation of Tunneling Effect for a N-Type Feedback Field-Effect Transistor

In this paper, the tunneling effect for a N-type feedback field-effect transistor (NFBFET) was investigated. The NFBFET has highly doped N-P junction in the channel region. When drain-source voltage is applied at the NFBFET, the aligning between conduction band of N-region and valence band of P-region occur, and band-to-band tunneling (BTBT) current can be formed on surface region of N-P junction in the channel of the NFBFET. When the doping concentration of gated-channel region (N_gc) is 4 × 10¹⁸ cm^-3, the tunneling current makes off-currents increase approximately 10⁴ times. As gate-source voltage is applied to NFBFET, the tunneling rate decreases owing to reducing of aligned region between bands by stronger gate-field. Eventually, the tunneling currents are vanished at the BTBT vanishing point before threshold voltage. When N_gc increase from 4 × 10¹⁸ to 6 × 10¹⁸, the tunneling current is generated not only at the surface region but also at the bulk region. Moreover, the tunneling length is shorter at the surface and bulk regions, and hence the leakage currents more increase. The BTBT vanishing point also increases due to increase of tunneling rates at surface and bulk region as N_gc increases.

Dirac-source diode with sub-unity ideality factor

An increase in power consumption necessitates a low-power circuit technology to extend Moore’s law. Low-power transistors, such as tunnel field-effect transistors (TFETs), negative-capacitance field-effect transistors (NC-FETs), and Dirac-source field-effect transistors (DS-FETs), have been realised to break the thermionic limit of the subthreshold swing (SS). However, a low-power rectifier, able to overcome the thermionic limit of an ideality factor (η) of 1 at room temperature, has not been proposed yet. In this study, we have realised a DS diode based on graphene/MoS₂/graphite van der Waals heterostructures, which exhibits a steep-slope characteristic curve, by exploiting the linear density of states (DOSs) of graphene. For the developed DS diode, we obtained η < 1 for more than four decades of drain current (η_{ave_4dec} < 1) with a minimum value of 0.8, and a rectifying ratio exceeding 10⁸. The realisation of a DS diode represents an additional step towards the development of low-power electronic circuits.

While different types of low-power transistors have been investigated, low voltage rectifiers able to overcome the thermionic limit have not been proposed yet. Here, the authors report the realization of Dirac-source diodes based on graphene/MoS2/graphite heterostructures, showing ideality factors <1 and rectifying ratios exceeding 10⁸ at room temperature.

Atomic and structural modifications of two-dimensional transition metal dichalcogenides for various advanced applications

Two-dimensional (2D) transition metal dichalcogenides (TMDs) and their heterostructures have attracted significant interest in both academia and industry because of their unusual physical and chemical properties. They offer numerous applications, such as electronic, optoelectronic, and spintronic devices, in addition to energy storage and conversion. Atomic and structural modifications of van der Waals layered materials are required to achieve unique and versatile properties for advanced applications. This review presents a discussion on the atomic-scale and structural modifications of 2D TMDs and their heterostructures via post-treatment. Atomic-scale modifications such as vacancy generation, substitutional doping, functionalization and repair of 2D TMDs and structural modifications including phase transitions and construction of heterostructures are discussed. Such modifications on the physical and chemical properties of 2D TMDs enable the development of various advanced applications including electronic and optoelectronic devices, sensing, catalysis, nanogenerators, and memory and neuromorphic devices. Finally, the challenges and prospects of various post-treatment techniques and related future advanced applications are addressed.

Energy-Efficient III-V Tunnel FET-Based Synaptic Device with Enhanced Charge Trapping Ability Utilizing Both Hot Hole and Hot Electron Injections for Analog Neuromorphic Computing

A charge trap device based on field-effect transistors (FET) is a promising candidate for artificial synapses because of its high reliability and mature fabrication technology. However, conventional MOSFET-based charge trap synapses require a strong stimulus for synaptic update because of their inefficient hot-carrier injection into the charge trapping layer, consequently causing a slow speed operation and large power consumption. Here, we propose a highly efficient charge trap synapse using III-V materials-based tunnel field-effect transistor (TFET). Our synaptic TFETs present superior subthreshold swing and improved charge trapping ability utilizing both carriers as charge trapping sources: hot holes created by impact ionization in the narrow bandgap InGaAs after being provided from the p⁺-source, and band-to-band tunneling hot electrons (BBHEs) generated at the abrupt p⁺n junctions in the TFETs. Thanks to these advances, our devices achieved outstanding efficiency in synaptic characteristics with a 5750 times faster synaptic update speed and 51 times lower sub-fJ/um² energy consumption per single synaptic update in comparison to the MOSFET-based synapse. An artificial neural network (ANN) simulation also confirmed a high recognition accuracy of handwritten digits up to ∼90% in a multilayer perceptron neural network based on our synaptic devices.

All-Optical Reconfigurable Electronic Memory in a Graphene/SrTiO3 Heterostructure

Direct optical data coding in an electronic device is meaningful for photonic technology. Herein, we report electronic memory in a graphene/SrTiO₃ heterostructure, which presents the all-optical logic operation (encoding and decoding). The underlying physics have been elucidated in which the synergistic effect of surface localization with interface band bending is responsible for optical encoding and decoding in the electronic memory device of the graphene/SrTiO₃ heterostructure. Further, we demonstrate a robust retention and synaptic-like processing of optical signals, which may lead to significant applications in neuromorphic imaging sensors.

Pico-Watt Scanning Thermal Microscopy for Thermal Energy Transport Investigation in Atomic Materials

The thermophysical properties at the nanoscale are key characteristics that determine the operation of nanoscale devices. Additionally, it is important to measure and verify the thermal transfer characteristics with a few nanometer or atomic-scale resolutions, as the nanomaterial research field has expanded with respect to the development of molecular and atomic-scale devices. Scanning thermal microscopy (SThM) is a well-known method for measuring the thermal transfer phenomena with the highest spatial resolution. However, considering the rapid development of atomic materials, the development of an ultra-sensitive SThM for measuring pico-watt (pW) level heat transfer is essential. In this study, to measure molecular- and atomic-scale phenomena, a pico-watt scanning thermal microscopy (pW-SThM) equipped with a calorimeter capable of measuring heat at the pW level was developed. The heat resolution of the pW-SThM was verified through an evaluation experiment, and it was confirmed that the temperature of the metal line heater sample could be quantitatively measured by using the pW-SThM. Finally, we demonstrated that pW-SThM detects ultra-small differences of local heat transfer that may arise due to differences in van der Waals interactions between the graphene sheets in highly ordered pyrolytic graphite. The pW-SThM probe is expected to significantly contribute to the discovery of new heat and energy transfer phenomena in nanodevices and two-dimensional materials that have been inaccessible through experiments.